On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
> Signed-off-by: Rich Felker <dalias@xxxxxxxx>
> ---
> .../bindings/interrupt-controller/jcore,aic.txt | 29 ++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> new file mode 100644
> index 0000000..5dc99b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> @@ -0,0 +1,29 @@
> +J-Core Advanced Interrupt Controller
> +
> +Required properties:
> +
> +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
> + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> + the "aic2" core with 64 interrupts.
> +
> +- reg : Memory region for configuration.
> +
> +- interrupt-controller : Identifies the node as an interrupt controller
> +
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> + interrupt source. The value shall be 1.
> +
> +Optional properties:
> +
> +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> + configuration, to be scaled by the cpu number.
I take is that "cpu number" means the "sequential, zero-based hardware
cpu id" defined in patch 2. I would recommend that you explicitly
mention that (e.g. here say "hardware cpu id" rather than "cpu number"),
so as to not have this confused with Linux logical IDs.
Thanks,
Mark.
> +
> +
> +Example:
> +
> +aic: interrupt-controller@200 {
> + compatible = "jcore,aic2";
> + reg = < 0x200 0x10 >;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +};
> --
> 2.8.1
>
>
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