On 05/17/2016 09:48 AM, Xinliang Liu wrote:
On 17 May 2016 at 11:43, Archit Taneja <architt@xxxxxxxxxxxxxx> wrote:
On 05/16/2016 05:31 PM, Laurent Pinchart wrote:
Hi Archit,
On Friday 22 Apr 2016 11:10:18 Archit Taneja wrote:
On 04/22/2016 04:02 AM, Laurent Pinchart wrote:
On Wednesday 09 Mar 2016 16:27:18 Archit Taneja wrote:
Add description of ADV7533. Add the required and optional properties
that
are specific to it.
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: Rob Herring <robh@xxxxxxxxxx>
Signed-off-by: Archit Taneja <architt@xxxxxxxxxxxxxx>
---
.../bindings/display/bridge/adi,adv7511.txt | 25
++++++++++++-----
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git
a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
index
96c25ee..420da5a 100644
--- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
+++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
[snip]
+- adi,disable-timing-generator: Only for ADV7533. Disables the
internal
timing
+ generator. The chip will rely on the sync signals in the DSI data
lanes,
+ rather than generate its own timings for HDMI output.
Isn't that something that should be selectable at runtime ?
The timing generator can be enabled/disabled at runtime. Although, we
don't have a way to tell the driver whether we want to keep it enabled
or not.
It's a hardware feature that works well on most platforms, but not on
all. In particular, it works well on DB410c, but causes issues with
the Hikey 96 board. The DSI host on Hikey has different clock sources
that generate the display controller's pixel clock and DSI byte clock,
whereas the Qualcomm SoC uses the same source. My guess is that the
ADV7533's timing generator doesn't like it when the pixel data and
clock are out of phase or something.
Since it is a hardware feature which needs tweaking, I thought it
qualified as a DT property.
The fact that a hardware generator is present is certainly describes the
hardware, but I'm not sure whether to enable it or not also qualifies as a
hardware feature.
Are there use cases for using the timing generator conditionally on a
given
board ? As you implement support for disabling it, I assume it's not
mandatory. What feature(s) do we lose if we keep it disabled ?
The spec says it's recommended to use the internal timing generator. In
the case of db410c, I observe an unstable output/flicker for certain
modes if I don't enable it.
In the case of hikey platform, it's the other way round.
Xinliang, could you describe the problems you face when the timing
generator is enabled?
Yes, opening the timing generator of ADV7533 can benefit the HDMI
output signal.
But, for some circumstances, we need to disable timing generator:
To make modes work, the timing parameters (hfp, hbp, etc.) used by
ADV7533 timing generator should match the ones used in DSI.
If the timing parameters changed in DSI and these changing timing
parameters can't pass to ADV7533, then it need to disable the timing
generator of ADV7533 to make mode work.
Some modes in HiKey is in this case.
The ADV7533 chip's DSI receiver supports the DSI Video mode
sub-mode: "Non-burst Mode with sync pulses". Ideally, a DSI
receiver supporting this mode should be able to reconstruct
the timings using packets embedded in the controller.
With DB410c, it seems to struggle without it, and with
Hikey, we need to explicitly disable it because, as I understand,
the DSI controller there tweaks some of the timings parameters
in the mode it wants to set.
It would have been ideal to not expose this knob in DT, but
we need it for ADV7533 to work across multiple platforms.
Laurent, do you have any more thoughts on this? I'd posted
out a v4 of this patch set. Please have a look when you get
the chance.
Thanks,
Archit
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