Enable FPGA's IRQ controller. It is in charge of dispatching interrupts
generated by IPs in the FPGA. The SoC is notified that an interrupt
occurred through a GPIO.
Signed-off-by: Damien Riegel <damien.riegel@xxxxxxxxxxxxxxxxxxxx>
---
arch/arm/boot/dts/imx51-ts4800.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts
index 0ff76a1..2c89988 100644
--- a/arch/arm/boot/dts/imx51-ts4800.dts
+++ b/arch/arm/boot/dts/imx51-ts4800.dts
@@ -149,6 +149,19 @@
#size-cells = <1>;
ranges = <0 0 0 0x1d000>;
+ fpga_irqc: fpga_irqc@0,15000 {
+ compatible = "technologic,ts4800-irqc";
+ reg = <0x15000 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_interrupt_fpga>;
+
+ interrupt-parent = <&gpio2>;
+ interrupts= <9 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
syscon: syscon@b0010000 {
compatible = "syscon", "simple-mfd";
reg = <0x10000 0x3d>;
@@ -228,6 +241,12 @@
>;
};
+ pinctrl_interrupt_fpga: fpgaicgrp {
+ fsl,pins = <
+ MX51_PAD_EIM_D27__GPIO2_9 0xe5
+ >;
+ };
+
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
--
2.5.0
--
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