On 3 May 2016 at 18:43, Tony Lindgren <tony@xxxxxxxxxxx> wrote: > Does a fixed divider calculation of input * (32768 / 27e6) make sense > here too as pointed out earlier by Matthijs for the ti81xx? That was an actual fractional divider, i.e. the output clock would be exactly that ratio of the input clock, which would therefore yield 32768 Hz if the default crystal is used for the main osc. It makes no sense to use it to describe a wobbly RC osc. On 3 May 2016 at 19:32, Tero Kristo <t-kristo@xxxxxx> wrote: > Also, as it is security related, this is kind of sensitive area to discuss publicly. Don't be silly. The only sense in which this clock is "security related" is because it's used for the secure watchdog, and the reason to use it despite its inaccuracy is completely obvious: an internal rc osc can't be easily manipulated by an external attacker. I see no reason to act all cloak-and-dagger about this. (This seems to be a general theme to conceal "security related" things from public documentation. If I were an HS customer I'd actually be concerned about such behaviour since it would seem to indicate a lack of confidence in one's security architecture.) Matthijs -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
