* Peter Ujfalusi <peter.ujfalusi@xxxxxx> [160415 12:52]: > On 04/15/2016 06:16 PM, Tony Lindgren wrote: > >> We can hack this around by adding HWMOD_NO_IDLEST to the sidetone hwmod I > >> guess. As the sidetone does not have PRCM level control - it is part of McBSP. > > > > Heh if they are using the same register bits for two separate modules, > > then that's a bug for sure :) I think the sidetone module only has the > > clock gating bit in the ST_SYSCONFIG. > > Yes, the sidetone only has clock gating bit in ST_SYSCONFIG, but the hwmod has > the prcm section which is identical of the corresponding McBSP hwmod prcm section. > > Since we have only one MCBSP2_ICLK and only one bit in PRCM registers for it, > this is a bug in the hwmod data for sure. Only the mcbsp hwmod should have > prcm section and the sidetone hwmod is not needed IMO: > It is a bug to have sidetone enabled when McBSP is not enabled and configured > properly. The sidetone can not work w/o proper McBSP configuration. > > If we were to keep both hwmods and add new set of pm_runtime calls for the > mcbsp.sidetone, it will only increase/decrease the mcbsp_iclk enable count. It > must never enable the clock itself since that is a bug in the SW. OK makes sense. I'd prefer to keep it to match the hardware for the modules. > > Then all these modules just sit on the L4 interconnet at > > separate targets, including the clockdomain. > > The McBSPi core and it's sidetone is in the same clock domain as the sidetone > is using the McBSPi interface clock. It is kind of a leech ;) Well they still are able to use the McBSP interface clock independently AFAIK :) Tony -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
