On Mon, Apr 18, 2016 at 04:51:44PM +0200, Thierry Reding wrote: > From: Thierry Reding <treding@xxxxxxxxxx> > > The XUSB pad controller allows PCIe lanes to be controlled individually, > providing fine-grained control over their power state. Previous attempts > at describing the XUSB pad controller in DT had erroneously assumed that > all PCIe lanes were driven by the same PHY, and hence the PCI host > controller would reference only a single PHY. > > Moving to a representation of per-lane PHYs requires that the operating > system driver for the PCI host controller have access to the set of PHY > devices that make up the connection of each root port in order to power > up and down all of the lanes as necessary. > > Acked-by: Rob Herring <robh@xxxxxxxxxx> > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx> > --- > Changes in v5: > - add per-SoC examples to clarify what properties are relevant on each > generation > - clarify the rationale for moving the per-lane PHYs > > Changes in v4: > - add additional lanes subnode when dereferencing PHYs from the XUSB pad > controller to reflect changes in its binding > > .../bindings/pci/nvidia,tegra20-pcie.txt | 224 ++++++++++++++++++++- > 1 file changed, 219 insertions(+), 5 deletions(-) Hi Bjorn, I think I've requested this before, but in case I didn't: once you're happy with these changes, I'd like to take them through the Tegra tree to resolve the dependencies with the remainder of a series that involves the pinctrl and PHY drivers as well as devicetree changes. In order to do so I'm looking for an Acked-by. Once applied I can provide a stable branch containing the dependencies for you to pull into the PCI tree if necessary. Thierry
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