On 04/15/2016 02:39 AM, Laxman Dewangan wrote:
On Friday 15 April 2016 01:38 PM, Linus Walleij wrote:
On Tue, Apr 12, 2016 at 4:56 PM, Laxman Dewangan
<ldewangan@xxxxxxxxxx> wrote:
NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
or 3.3V I/O voltage levels. Also the IO pads can be configured
for power down state if it is not used. SW needs to configure the
voltage level of IO pads based on IO rail voltage and its power
state based on platform usage.
The voltage and power state configurations of pads are provided
through pin control frameworks. Add pin control driver for Tegra's
IO pads' voltage and power state configurations.
Even if Tegra is not using the generic code for handling the
standard bindings (GENERIC_PINCONF) it doesn't stop
you from using the generic bindings and contributing to them.
Historically you have a few custom bindings like these:
nvidia,pins
nvidia,function
nvidia,pull
nvidia,tristate
etc etc, but that is just unfortunate and due to preceding the
generic bindings. I would appreciate if you started to support
the generic bindings in parallel, but I'm not gonna push that issue.
Yaah, these are in my plate to cleanup. Let me work with Stephen, what
he think here.
For existing chips, we must always support the existing bindings.
There's no point moving to the new bindings since it'll just add more
code that just does the same thing.
For new chips perhaps it makes sense to move to the new standardized
properties. That said, I don't expect we'll need pinmux on those chips
since it's guaranteed that FW will set up the static pinmux, and HW
explicitly doesn't support dynamic pinmuxing?
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