If Davinci AEMIF is used we don't need to set timings and bus width.
It is done by AEMIF driver (drivers/memory/davinci-aemfi.c).
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@xxxxxx>
---
drivers/mtd/nand/davinci_nand.c | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 4705214..879e915 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -742,27 +742,35 @@ static int __init nand_davinci_probe(struct platform_device *pdev)
goto err_clk_enable;
}
+#if !IS_ENABLED(CONFIG_TI_DAVINCI_AEMIF)
/*
- * Setup Async configuration register in case we did not boot from
- * NAND and so bootloader did not bother to set it up.
+ * Setup Async configuration register in case we did not boot
+ * from NAND and so bootloader did not bother to set it up.
*/
- val = davinci_nand_readl(info, A1CR_OFFSET + info->core_chipsel * 4);
+ val = davinci_nand_readl(info, A1CR_OFFSET +
+ info->core_chipsel * 4);
- /* Extended Wait is not valid and Select Strobe mode is not used */
+ /*
+ * Extended Wait is not valid and Select Strobe mode is not
+ * used
+ */
val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
if (info->chip.options & NAND_BUSWIDTH_16)
val |= 0x1;
- davinci_nand_writel(info, A1CR_OFFSET + info->core_chipsel * 4, val);
+ davinci_nand_writel(info, A1CR_OFFSET +
+ info->core_chipsel * 4, val);
ret = 0;
if (info->timing)
- ret = davinci_aemif_setup_timing(info->timing, info->base,
- info->core_chipsel);
+ ret = davinci_aemif_setup_timing(info->timing,
+ info->base,
+ info->core_chipsel);
if (ret < 0) {
dev_dbg(&pdev->dev, "NAND timing values setup fail\n");
goto err;
}
+#endif
spin_lock_irq(&davinci_nand_lock);
--
1.7.9.5
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