Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up the first Cortex-A15 CPU core and the Cortex-A15 L2 cache/SCU to
their respective PM domains.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
v2:
- Change one-line summary prefix to match current arm-soc practices,
- Update compatible values.
---
arch/arm/boot/dts/r8a7793.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 9a30f650aa515b80..843fd3306f35ebb0 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -43,6 +43,7 @@
voltage-tolerance = <1>; /* 1% */
clocks = <&cpg_clocks R8A7793_CLK_Z>;
clock-latency = <300000>; /* 300 us */
+ power-domains = <&pd_ca15_cpu0>;
/* kHz - uV - OPPs unknown yet */
operating-points = <1500000 1000000>,
@@ -57,6 +58,7 @@
L2_CA15: cache-controller@0 {
compatible = "cache";
+ power-domains = <&pd_ca15_scu>;
cache-unified;
cache-level = <2>;
};
@@ -1144,6 +1146,43 @@
};
};
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7793-sysc", "renesas,rcar-gen2-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+
+ pm-domains {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pd_ca15_scu: scu@12 {
+ reg = <12 0x180>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #power-domain-cells = <0>;
+
+ pd_ca15_cpu0: cpu@0 {
+ reg = <0 0x40>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_ca15_cpu1: cpu@1 {
+ reg = <1 0x41>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ pd_sh: sh@16 {
+ reg = <16 0x80>;
+ #power-domain-cells = <0>;
+ };
+
+ pd_sgx: sgx@20 {
+ reg = <20 0xc0>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
ipmmu_sy0: mmu@e6280000 {
compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
reg = <0 0xe6280000 0 0x1000>;
--
1.9.1
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