On 02.02.2016 02:52, Eric Anholt wrote:
Eric Anholt <eric@xxxxxxxxxx> writes:
kernel@xxxxxxxxxxxxxxxx writes:
From: Martin Sperl <kernel@xxxxxxxxxxxxxxxx>
Testing with different clock divider values has shown
that (at least for the PCM clock) the clock divider
has to be at least 2, otherwise the clock will not
output a signal.
For a MASH clock (PWM, PCM, SLIMBUS, but not the others), the minimum
integer component of the divider is:
mash 0: 1
mash 1: 2
mash 2: 3
mash 3: 5
More specific MASH list:
GP0
GP1
(*not* gp2)
PCM
PWM
SLIM
I got the list from the broadcom provided headers for the VC4.
and where CM_*_DIV range does not start at 12 we have a fractional
divider (also requires if CM_*_FRAC or CM_*_MASH is set)
And if CM_*_MASH is set we got a mash enabled clock:
CM_GNRICCTL_MASH
CM_GP0CTL_MASH
CM_GP1CTL_MASH
CM_PCMCTL_MASH
CM_PWMCTL_MASH
CM_SLIMCTL_MASH
And this is what can get implemented by configuring mash
in the DT - otherwise only frac (a.k.a. MASH = 1) is
used for any clock that has .frac_bits > 0.
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