Thomas Petazzoni wrote:
if panic is enabled : >|--------WOR-------WS0--------WOR-------WS1 >|------timeout------(panic)------timeout-----reset
I'm quite certainly missing something completely obvious here, but how can you get the WS1 interrupt*after* raising a panic? Aren't all interrupts disabled and the system fully halted once you get a panic(), especially when raised from an interrupt handler? If that's the case, how can the system continue to do things, such as receiving the WS1 interrupt and resetting ?
Typically, WS1 is not an interrupt. Instead, it's a hard system-level reset.
The hardware is capable of generating an interrupt for both WS0 and WS1. However, the ACPI table only contains one interrupt value, and it's not clear whether that's supposed to be the WS0 interrupt or the WS1 interrupts.
So this whole thing does assume a specfic watchdog configuration. -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
