On Wed, Jan 06, 2016 at 04:29:08PM +0530, Kishon Vijay Abraham I wrote: > DRA72 uses USB3 PHY for the 2nd lane of PCIE. The configuration > required to make USB3 PHY used for the 2nd lane of PCIe is done > here. > > Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx> > --- > Documentation/devicetree/bindings/phy/ti-phy.txt | 2 ++ > drivers/phy/phy-ti-pipe3.c | 30 +++++++++++++++++++++- > 2 files changed, 31 insertions(+), 1 deletion(-) Acked-by: Rob Herring <robh@xxxxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
