dra72 reuse the USB PHY for the PCIe 2n lane. So in order for PCIe x2 mode to work in dra72, certain special configuration has to be made in USB PHY. This patch series adds those configurations. In order to enable PCIe x2 mode in DRA72, USB should be disabled. Certain board modifications has to be done in order to test x2 mode in dra72-evm. Patch series is rebased on top of linux-phy next Kishon Vijay Abraham I (2): phy: ti-pipe3: get tx and rx MEM resource phy: ti-pipe3: configure usb3 phy to be used as pcie phy Documentation/devicetree/bindings/phy/ti-phy.txt | 2 + drivers/phy/phy-ti-pipe3.c | 57 +++++++++++++++++++++- 2 files changed, 58 insertions(+), 1 deletion(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
