Hi Geert, On Thursday 19 November 2015 21:44:27 Geert Uytterhoeven wrote: > On Thu, Nov 19, 2015 at 9:26 PM, Laurent Pinchart wrote: > > On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote: > >> Amend the DT bindings to include the optional clock sources for the Baud > >> Rate Generator for External Clock (BRG), as found on some SCIF variants > >> and on HSCIF. > >> > >> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > >> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > >> > >> @@ -46,6 +46,12 @@ Required properties: > >> On (H)SCI(F) and some SCIFA, an additional clock may be specified: > >> - "hsck" for the optional external clock input (on HSCIF), > >> - "sck" for the optional external clock input (on other variants). > >> > >> + On UARTs equipped with a Baud Rate Generator for External Clock > >> (BRG) > >> + (some SCIF and HSCIF), additional clocks may be specified: > >> + - "int_clk" for the optional internal clock source for the > >> frequency > >> + divider (typically the (AXI or SHwy) bus clock), > > > > Isn't this always the same clock as the SCIF functional clock ? > > (On R-Car Gen2/3) > > No, SCIF uses different parents for fck (p) and int_clk (zs). Right, my bad. Should we rename "int_clk" to something that makes it explicit that the clock is used as the BRG-EC input ? Maybe brg_clk, int_brg, int_brg_clk ? We probably don't need to keep the _clk suffix as it's quite evident that a clock name refers to a clock. > HSCIF uses the same parents though (zs). -- Regards, Laurent Pinchart -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
