On Fri, Nov 13, 2015 at 04:08:53PM +0800, Chen-Yu Tsai wrote: > On Mon, Nov 9, 2015 at 12:18 PM, Chen-Yu Tsai <wens@xxxxxxxx> wrote: > > On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard > > <maxime.ripard@xxxxxxxxxxxxxxxxxx> wrote: > >> The Allwinner SoCs have a gate controller to gate the access to the DRAM > >> clock to the some devices that need to access the DRAM directly (mostly > >> display / image related IPs). > >> > >> Use a simple gates driver to support it. > >> > >> Signed-off-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> > > > > Acked-by: Chen-Yu Tsai <wens@xxxxxxxx> > > > >> --- > >> drivers/clk/sunxi/clk-simple-gates.c | 2 ++ > >> 1 file changed, 2 insertions(+) > >> > >> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c > >> index 0214c6548afd..5666c767fa14 100644 > >> --- a/drivers/clk/sunxi/clk-simple-gates.c > >> +++ b/drivers/clk/sunxi/clk-simple-gates.c > >> @@ -112,6 +112,8 @@ CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk", > >> sunxi_simple_gates_init); > >> CLK_OF_DECLARE(sun5i_a13_apb1, "allwinner,sun5i-a13-apb1-gates-clk", > >> sunxi_simple_gates_init); > >> +CLK_OF_DECLARE(sun5i_a13_dram, "allwinner,sun5i-a13-dram-gates-clk", > >> + sunxi_simple_gates_init); > > Nit: Since the compatible added is sun5i, could you mention it in the > commit message, > to avoid confusion when we do this for the other families? It will be fixed in the v2. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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