Hi, Rob Herring <robh@xxxxxxxxxx> writes: > On Wed, Nov 18, 2015 at 06:20:31PM +0530, Subbaraya Sundeep Bhatta wrote: >> This patch adds binding doc for Xilinx DWC3 glue driver. >> >> Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta@xxxxxxxxxx> > > I really dislike how the DWC3 binding has been done. The sub-node here > is pointless. The only thing the outer node does is add clocks which > should simply be part of the DWC3 node. Presumably the IP block needs > some clocks... > > Anyway, it's self-contained within the DWC3, so I won't make you clean > up the mess. heh, it's definitely not pointless. We get a lot of free goodies by doing it that way. I'm just not going to repeat it once again. But in summary: a) we force people to write glue layers for *only* their HW specific details b) there's really no way to abuse dwc3 core because there's no symbol exported from dwc3 core to glue c) PM (both system sleep and runtime) becomes a lot simpler with core only caring about what PM details delivered by SNPS (e.g. Hibernation mode from DWC3) and glue only has to consider the SoC integration parts of PM (for OMAP that would be PRCM details, hwmod, etc). I'm definitely not going to change dwc3 because it has made my life a lot saner. Definitely a lot saner than MUSB. Besides, DTS is supposed to describe the HW and that's, really, how the HW is. There's a piece of HW which is somewhat platform agnostic and delivered by SNPS as a black box (SNPS customers don't touch SNPS RTL) and there's another piece of HW which bridges this dwc3 to the platform specific details and integration context of the platform (for OMAP that would the SYSCONFIG/SYSSTATUS registers, Clock autogating, PRCM, etc, etc etc). So you _do_ in fact, have two separate pieces of HW which are SW visible and controllable independently. They each have their own IRQs (though in some SoCs they share the same line), they're own address space, yada yada yada. cheers -- balbi
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