On Mon, 3 Feb 2025 08:47:50 -0600 Rob Herring <robh@xxxxxxxxxx> wrote: > On Mon, Feb 3, 2025 at 6:05 AM Alireza Sanaee > <alireza.sanaee@xxxxxxxxxx> wrote: > > > > For L1 cache to be shared between SMT threads, a register array > > must be used. This, however, is not straightforward if every node > > in the CPU map refers to a separate CPU node. Therefore, it is > > suggested to create a separate CPU node for every SMT thread. The > > L1 cache can be shared if an extra node represents it. > > I don't understand why a cpu-map is a problem for the SMT case? > > I don't think this change is necessary. > > Rob Hi Rob, I posted the following patch, which uses a reg array to represent threads, allowing threads to share resources within a CPU node using reg array and without requiring an extra l1-cache layer: https://lore.kernel.org/all/20250110161057.445-1-alireza.sanaee@xxxxxxxxxx/
