On Mon, Feb 3, 2025 at 6:05 AM Alireza Sanaee <alireza.sanaee@xxxxxxxxxx> wrote: > > For L1 cache to be shared between SMT threads, a register array must be > used. This, however, is not straightforward if every node in the CPU map > refers to a separate CPU node. Therefore, it is suggested to create a > separate CPU node for every SMT thread. The L1 cache can be shared if an > extra node represents it. I don't understand why a cpu-map is a problem for the SMT case? I don't think this change is necessary. Rob
