Re: mempool and cacheline ping pong

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Hi Loïc:
I just took a quick look, was surprised to see no contention, and then realized that this was done on an AMD server.   AMD never added their support for the low level perf events that are similar to Intel's PEBS events.  The AMD cpus do have those similar features, and we've talked with them about getting them added to the perf tool, but so far we've not seen it.

I'm sorry if I didn't stress the "Intel" piece strongly enough.

Can you find an Intel server to rerun this test?   Any Intel server in the last 10 years (Ivy Bridge or newer) should work.  However for this testing, the newer and faster the server is, the more pronounced the contention will be.  So if you can get on a Cascade Lake or Skylake server, that would be best.

Joe
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