On 11/12/2012 03:24 PM, Mike Turquette wrote:
> Quoting Mark Langsdorf (2012-11-07 10:32:42)
>> The highbank clock will glitch with the current code if the
>> clock rate is reset without relocking the PLL. Program the PLL
>> correctly to preven glitches.
>>
>> Signed-off-by: Mark Langsdorf <mark.langsdorf@xxxxxxxxxxx>
>> Signed-off-by: Rob Herring <rob.herring@xxxxxxxxxxx>
>> Cc: mturquette@xxxxxxxxxx
>
> Hi Mark,
>
> Looks fine to me.
>
> I seem to be missing the rest of this series in my mail. Did you want
> me to take only this patch (2/6) into clk-next or were you only looking
> for my ACK?
The entire series enables highbank cpufreq. Would you normally take this
patch through cpufreq-next with an ACK or directly through clk-next?
--Mark Langsdorf
Calxeda, Inc.
>> ---
>> Changes from v3
>> Changelog text and patch name now correspond to the actual patch
>> was clk, highbank: remove non-bypass reset mode
>> Changes from v2
>> None
>> Changes from v1:
>> Removed erroneous reformating.
>>
>> drivers/clk/clk-highbank.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
>> index 52fecad..3a0b723 100644
>> --- a/drivers/clk/clk-highbank.c
>> +++ b/drivers/clk/clk-highbank.c
>> @@ -182,8 +182,10 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
>> reg |= HB_PLL_EXT_ENA;
>> reg &= ~HB_PLL_EXT_BYPASS;
>> } else {
>> + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
>> reg &= ~HB_PLL_DIVQ_MASK;
>> reg |= divq << HB_PLL_DIVQ_SHIFT;
>> + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
>> }
>> writel(reg, hbclk->reg);
>>
>> --
>> 1.7.11.7
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