> > I did an overview, back in 2007, of AMD and Intel processors that had > either tsc rate depending on P state and/or tsc rate changed by idle > and/or tsc values influenced by STPCLK-Throttling. Here are some > notes, along with pointers to the reference documents (please excuse > the ad-hoc style of these notes): > > http://git.dorsal.polymtl.ca/?p=lttv.git;a=blob_plain;f=doc/developer/tsc.txt > > So I might be missing something about your statement "all hardware > that does coordination between cores/etc like this also has a tsc > that is invariant of the actual P state.". Do you mean that all > udelay callers do not rely on it to provide a guaranteed lower-bound, > except for some sub-architectures ? ok there's basically 3 cases Case 1: single core, no hyperthreading. It does not matter what tsc does, since the kernel knows what it does and will either scale it or not for udelay depending on that. (this case includes single core SMP configurations) Case 2: multi core or HT, TSC is variable with CPU frequency. This is the really sucky case, since logical CPU 0's tsc frequency in part depends on what logical CPU 1 will do etc. No good answer for this other than assuming the worst. Based on your document these do actually exist in early P4 cpus. Case 3: multi core/HT but with fixed rate TSC; no problem whatsoever, tsc is a good measure for udelay. Only case 2 sucks :-( -- Arjan van de Ven Intel Open Source Technology Centre For development, discussion and tips for power savings, visit http://www.lesswatts.org -- To unsubscribe from this list: send the line "unsubscribe cpufreq" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
