* Arjan van de Ven (arjan@xxxxxxxxxxxxx) wrote: > On Fri, 23 Apr 2010 14:40:42 -0400 > Mathieu Desnoyers <mathieu.desnoyers@xxxxxxxxxxxx> wrote: > > > [CCing Arjan, who seems to have played a lot with ondemand lately] > > > > * Saravana Kannan (skannan@xxxxxxxxxxxxxx) wrote: > > > Resending email to "cc" the maintainers. > > > > > > Maintainers, > > > > > > Any comments? > > > > > > -Saravana > > > > > > Saravana Kannan wrote: > > >> Hi, > > >> > > >> I think there are a couple of issues with cpufreq and udelay > > >> interaction. But that's based on my understanding of cpufreq. I > > >> have worked with it for sometime now, so hopefully I not > > >> completely wrong. So, I will list my assumptions and what I think > > >> is/are the issue(s) and their solutions. > > >> > > >> Please correct me if I'm wrong and let me know what you think. > > >> > > >> Assumptions: > > >> ============ > > >> * Let's assume ondemand governor is being used. > > >> * Ondemand uses one timer per core and they have CPU affinity set. > > >> * For SMP, CPUfreq core expects the CPUfreq driver to adjust the > > >> per-CPU jiffies. > > >> * P1 indicates for lower CPU perfomance levels and P2 indicates a > > >> much higher CPU pref level (say 10 times faster). > > >> > > > so in reality, all hardware that does coordination between cores/etc > like this also has a tsc that is invariant of the actual P state. > If there are exceptions, those have a problem, but I can't think of any > right now. > Once the TSC is invariant of P state, udelay() is fine, since that goes > of the tsc, not of some delay loop kind of thing.... I did an overview, back in 2007, of AMD and Intel processors that had either tsc rate depending on P state and/or tsc rate changed by idle and/or tsc values influenced by STPCLK-Throttling. Here are some notes, along with pointers to the reference documents (please excuse the ad-hoc style of these notes): http://git.dorsal.polymtl.ca/?p=lttv.git;a=blob_plain;f=doc/developer/tsc.txt So I might be missing something about your statement "all hardware that does coordination between cores/etc like this also has a tsc that is invariant of the actual P state.". Do you mean that all udelay callers do not rely on it to provide a guaranteed lower-bound, except for some sub-architectures ? ARM currently does not rely on the c0_count register for udelay, but it could do it in a near future on the omap3 at least. This register follows the CPU frequency. I suspect that the current udelay loop implementation in arch/arm/lib/delay.S, being calibrated on loops_per_jiffy, does not work that well with ondemand cpufreq right now. Thanks, Mathieu -- Mathieu Desnoyers Operating System Efficiency R&D Consultant EfficiOS Inc. http://www.efficios.com -- To unsubscribe from this list: send the line "unsubscribe cpufreq" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
