On Thu, Jun 15, 2017 at 7:58 AM, Dave Hansen <dave.hansen@xxxxxxxxx> wrote: > On 06/14/2017 02:38 PM, Jerome Glisse wrote: >> On Wed, Jun 14, 2017 at 02:20:23PM -0700, Dave Hansen wrote: >>> On 06/14/2017 01:11 PM, Jérôme Glisse wrote: >>>> Cache coherent device memory apply to architecture with system bus >>>> like CAPI or CCIX. Device connected to such system bus can expose >>>> their memory to the system and allow cache coherent access to it >>>> from the CPU. >>> How does this interact with device memory that's enumerated in the new >>> ACPI 6.2 HMAT? That stuff is also in the normal e820 and, by default, >>> treated as normal system RAM. Would this mechanism be used for those >>> devices as well? >>> >>> http://www.uefi.org/sites/default/files/resources/ACPI_6_2.pdf >> It doesn't interact with that. HMM-CDM is a set of helper that don't >> do anything unless instructed so. So for device memory to be presented >> as HMM-CDM you need to hotplug it as ZONE_DEVICE(DEVICE_PUBLIC) which >> can be done with the helper introduced in patch 2 of this patchset. > [Removing my cc'd email id and responding from a different address] > I guess I'm asking whether we *should* instruct HMM-CDM to manage all > coherent device memory. If not, where do we draw the line for what we > use HMM-CDM, and for what we use the core MM? > If you believe the memory is managed by the device (and owned by a device driver) I'd suggest using HMM-CDM. The idea behind HMM-CDM was that it enables transparent migration of pages and its preferred when locality of computation and locality of memory access is the preferred model. The other model was N_COHERENT_MEMORY that used the core MM, but there were objections to exposing device memory using that technology. Balbir Singh. -- To unsubscribe from this list: send the line "unsubscribe cgroups" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
