On 06/14/2017 01:11 PM, Jérôme Glisse wrote: > Cache coherent device memory apply to architecture with system bus > like CAPI or CCIX. Device connected to such system bus can expose > their memory to the system and allow cache coherent access to it > from the CPU. How does this interact with device memory that's enumerated in the new ACPI 6.2 HMAT? That stuff is also in the normal e820 and, by default, treated as normal system RAM. Would this mechanism be used for those devices as well? http://www.uefi.org/sites/default/files/resources/ACPI_6_2.pdf -- To unsubscribe from this list: send the line "unsubscribe cgroups" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
