[OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0-> 4.1 update failing

[loony at loonybin.org (Peter Arremann)]

On Wednesday 29 June 2005 00:20, Feizhou wrote:
> I thought they have done away with the high memory bounce buffers?
Unfortunately AMD gets punished for Intel's lazyness. Intel does not want to 
implement an iommu. RedHat and others don't want to have to support two 
separate kernels - so they limit IO to the lowest 4GB no matter if you're 
running an Opteron or EM64T. 

> Can you explain what Andi means by this?
> ----quote----
> Current X86-64 implementations only support 40 bit of address space,
> but we support upto 46bits. This expands into MBZ space in the page tables.
>
> -Andi Kleen, Jul 2004
> ----quote----
I assume this quote is from http://lwn.net/Articles/117783/? about the 4th 
page table level? 
The memory that your process can use is split in several different segments as 
listed in that article. The processes need to have (among other stuff) access 
to the kernel, shared memory and so on. For that they have to select a 
mapping - and the mapping was simply selected to support 46 bits... 


> Does it mean that we don't need no fancy tweaks to get direct addressing
> for over 1G or over 4G?
>
> Is that hack for Athlons limited/useful only to Athlon MP boards with
> the Linux option in BIOS or do Opterons also need that?
No - opterons running in 64bit mode don't need any games to address more than 
4GB. 

Peter.