[OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0-> 4.1 update failing

[feizhou at graffiti.net (Feizhou)]

Bryan J. Smith <b.j.smith@xxxxxxxx> wrote:
> From: Robert Hanson <roberth@xxxxxxxxxxxx>
> 
>>or should i be more specific with the question(s)?
>>the reason i ask is that i just dumped 2 gig dram in a basic
>>P4 Intel 3.0GHz box to play with.
>>regards and TIA,
> 
> 
> At more than 1GiB on Linux/x86, you must use a 4G+4G kernel
> (this is the default) to see more than 960MiB.  This causes a
> signficant (10%+) performance hit.  On more than 4GiB, it is
> worsened as more extensive paging is used.
> 
> If you have 1GiB or less, you should rebuild with_out_ "HIGHMEM"
> support which is a 1G+3G kernel, and you'll see better performance
> (and memory will be limited to 960MiB).
> 

I thought they have done away with the high memory bounce buffers?

Can you explain what Andi means by this?
----quote----
Current X86-64 implementations only support 40 bit of address space,
but we support upto 46bits. This expands into MBZ space in the page tables.

-Andi Kleen, Jul 2004
----quote----

Does it mean that we don't need no fancy tweaks to get direct addressing 
for over 1G or over 4G?

Is that hack for Athlons limited/useful only to Athlon MP boards with 
the Linux option in BIOS or do Opterons also need that?