On Saturday 25 June 2005 16:18, Bryan J. Smith wrote:
> Dude, you're totally mis-appropriating simple board layout
> specifications to how the logic of the bus works. That's why I'm not
> even going to discuss this any longer.
Then enlighten me - if I have 40 address bits - transmit only the higher 37
since I don't need the lower end. Timing schemas show only one Input hold
time per address transfer for all available pins - how can that be a 32bit
bus? (ftp://download.intel.com/design/Xeon/datashts/30675401.pdf)
And, if timing diagrams, pinouts and so on lie about the size of the bus, what
is actually going on, then I guess its true - Intel uses voodoo magic to
design their chips and they added extra address pin, never ever use them and
the MCH figures out the missing address bits by some more ocult means
(http://www.amazon.com/exec/obidos/ASIN/B00001ZWV7/104-8776547-8655150)
And if its not, then your whole speach about the pae36 differences between a
gtl+ or ev6 connected device is wrong, which then in turn makes the only real
difference the iommu the newer athlon cores provide (so dma can go above the
first 4GB rather than having to be bounced)... This is also supported by the
intel, amd and redhat docs (see links posted above and in previous mails),
the post Feizhou made in this thread convering the LKML references about
using the apggart and even microsoft
(http://www.microsoft.com/whdc/system/platform/server/PAE/pae_os.mspx)
*shrugs* Intel, AMD and any other spec sheet you can find down to VIA chipset
docs agrees with that... But I guess I'm still wrong though?
Peter.
