[OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing

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On Saturday 25 June 2005 02:27, Bryan J. Smith wrote:
> The existence of an actual, physical
> trace is not how addressing works.
Then how does it work?  You always just tell me that's not how it is -  
without an exact reason why or offering an alternative that does not 
contradict the manufacturers documentation. You call it a 32bit bus, the rest 
of the world, including the guys that developed the bus, the guys that build 
mainboards based on it, the guys that illigaly make chipsets with a 
compatible protocol without a license - they all see it different. 

> But at this point, let's just forget this whole thread because it's
> obvious that you're not interested in hearing me out,
Valid to point out what you percive is the problem in us finding a solution.

> just hearing yourself out.
Personal attack - don't think that has anything to do with the technical 
problem. Its not even a very good attack. I'm the one who in almost all 
emails wrote less than you, plus I backed up my arguments with links to 
official standards or manufacturers documentation. 

Then again, I might have been using a technique that you're unfamiliar with. 
Its called devide and conquer. You start with a large problem that you're 
trying to solve. You then split this problem into several smaller ones and 
try to solve them. If nessecary, repeat this until you've reached a point 
where you can solve the simple problems and then you use these solutions as 
building blocks to go after the larger problem. This method is tought to, 
among others, programmers, electrical engineers and managers - so I assume 
its a more valid aproach than personal attacks :-)


But in the end I agree - lets drop this. Sorry if I came across that way - for 
me it was simply frustration. I started with a statement I did not understand 
and then each time all I got back was a "that's not how it works" - without 
any pointers to more documentation or anything. So I had to - using the 
method outlined above - dig down another layer, then an other and so on until 
we're at a level that we can both agree on. Then, at least that was the plan, 
go from a common ground up to what you claim is the way it works so we can 
figure out exactly who is wrong and where the error in thinking lays. 

Unfortunately I guess that won't be happening, because I simply can't accept 
that changes in the physical layout of a parallel bus do not have any effect 
on its width. SCSI did it when going from 8bit narrow to 16 bit wide. It 
worked for them. [http://pinouts.ru/data/info-scsi_pinout.shtml] MCA, usually 
a 32bit bus, had a low cost 16bit variant that did the same.
[http://pinouts.ru/data/mca_32bit_pinout.shtml] PCI? 32bit addressing but 
with the optional 64bit extension, has 64 address lines... 
[http://pinouts.ru/data/PCI_pinout.shtml] 

Peter.

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