[OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing

[loony at loonybin.org (Peter Arremann)]

On Friday 24 June 2005 22:22, Bryan J. Smith wrote:
> > Then you're clearly wrong calling it a 32bit addressed bus...
>
> _All_ GTL designs are physically 32-bit addressing buses.
> The use of 4-bit extra bits to do PAE36 is _not_ direct.

Hmmm... GTL is a parallel bus... Therefore the width of the bus is defined by 
either address or data width. GTL and all variants are 64bit data, so that 
can't be the reason for calling it a 32bit bus. 
Since the accesses have to be aligned on 8 byte boundries the lower the bus 
does not carry A0, A1, A2. 

On the Pentium (GTL bus) there are the address pins A3 through A31. [Pentium 
MMX embedded version, couldn't find the regular P5/P54C docs anymore. 
www.intel.com/design/intarch/applnots/27320602.pdf]

Then, GTL+, support for PAE36, has address bits for 36bit adressing - A3 
through A35. [Pentium II processor specs: 
ftp://download.intel.com/design/intarch/datashts/27326801.pdf] 

Finally you've got the high end stuff like a Xeon MP, 64bit... Address lines 
A3 through A39 - so space for 40 bit physical addresses. 
[http://download.intel.com/design/Xeon/datashts/30675401.pdf&e=7152]

So, if the different number of address lines doesn't change the width of a 
bus, what does? :-)

Peter.