On Fri, 2005-06-24 at 21:35 -0400, Peter Arremann wrote:
> Sorry I guess. Don't know how that happened - went to a electrical engineering
> school, specialized in micro electronics :-)
So you understand how memory controllers work then, correct?
You understand how memory can show up as half, quarter or incompatible
based on differences in IC, controller logic, etc..., correct?
> Ok, now I have to ask even more questions :-) If the physical bus is EV6, the
> internals are EV6 and the programming model doesn't matter as you said before
> - then why would the TLB on the athlon emulate a GTL?
Compatibility. Win32/PAE36 expects to be able to page 512MiB from above
4GiB into under 4GiB using the TLB.
> Then you're clearly wrong calling it a 32bit addressed bus...
_All_ GTL designs are physically 32-bit addressing buses.
The use of 4-bit extra bits to do PAE36 is _not_ direct.
> Define paging then - I can access >4GB on an EMT64 - It just lacks and IO mmu
> to do coordinate dma from a 32bit device to a memory region > 4GB... but if I
> just do a memory access, then there is no issue - no paging nessecary...
I'm not even talking about the I/O MMU anymore. I'm talking about
paging 512MB of memory from above 4GiB (PAE36) into 4GiB (32-bit).
GTL has to do it.
EV6, natively, does not.
> they solved the 32bit IO issue with by morphing their agpgart into a
> minimalistic io mmu ...
I'm not even talking about the I/O MMU anymore.
--
Bryan J. Smith b.j.smith@xxxxxxxx
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It is mathematically impossible for someone who makes more than you
to be anything but richer than you. Any tax rate that penalizes them
will also penalize you similarly (to those below you, and then below
them). Linear algebra, let alone differential calculus or even ele-
mentary concepts of limits, is mutually exclusive with US journalism.
So forget even attempting to explain how tax cuts work. ;->
