Alexei Starovoitov <alexei.starovoitov@xxxxxxxxx> writes: [...] > > +src > > + the source register number (0-10), except where otherwise specified > > + (`64-bit immediate instructions`_ reuse this field for other > > +purposes) > > There are more than one? > I guess we have such section now, > but in ISA it really is only one insn. LD_IMM64. > It's one insn for the interpreter and one insn for JITs. Here the plural is really referring to occurrences in programs, rather than implying multiple opcodes, so I don't think the grammar is incorrect. [...] > > +As discussed below in `64-bit immediate instructions`_, some > > +instructions use a 64-bit immediate value that is constructed as follows. > > +The 64 bits following the basic instruction contain a pseudo > > +instruction using the same format but with opcode, dst, src, and > > +offset all set to zero, and imm containing the high 32 bits of the immediate > value. > > 'instructions' here and further reads a bit odd. > May be calling it one instruction where imm_lo/hi have different semantics > depending on src would be better? I will reword the first sentence above to: As discussed below in `64-bit immediate instructions`_, a 64-bit immediate instruction uses a 64-bit immediate value that is constructed as follows. [...] > > > + > > +================= ================== > > +64 bits (MSB) 64 bits (LSB) > > +================= ================== basic instruction pseudo > > +instruction ================= ================== > > + > > +Thus the 64-bit immediate value is constructed as follows: > > + > > + imm64 = imm + (next_imm << 32) > > + > > +where 'next_imm' refers to the imm value of the pseudo instruction > > +following the basic instruction. > > + > > +In the remainder of this document 'src' and 'dst' refer to the values > > +of the source and destination registers, respectively, rather than the > register number. > > + > > Instruction classes > > ------------------- > > > > @@ -75,20 +114,24 @@ For arithmetic and jump instructions > > (``BPF_ALU``, ``BPF_ALU64``, ``BPF_JMP`` an ============== ====== > ================= > > 4 bits (MSB) 1 bit 3 bits (LSB) > > ============== ====== ================= -operation code source > > instruction class > > +code source instruction class > > ============== ====== ================= > > > > -The 4th bit encodes the source operand: > > feels wrong to lose this part. The concept is still in the document, just in the "Arithmetic and jump instructions" section since it seems specific to those (i.e., not the "Load and store instructions"). > > +code > > + the operation code, whose meaning varies by instruction class > > > > - ====== ===== ======================================== > > - source value description > > - ====== ===== ======================================== > > - BPF_K 0x00 use 32-bit immediate as source operand > > - BPF_X 0x08 use 'src_reg' register as source operand > > - ====== ===== ======================================== > > +source > > + the source operand location, which unless otherwise specified is one of: > > > > -The four MSB bits store the operation code. > > same here. Still there in the supersection. These are easier to see in the rendered document. Dave
