Hi Puranjay, On Sun, May 05, 2024 at 10:40:00PM GMT, Puranjay Mohan wrote: > Puranjay Mohan <puranjay@xxxxxxxxxx> writes: > > > The BPF atomic operations with the BPF_FETCH modifier along with > > BPF_XCHG and BPF_CMPXCHG are fully ordered but the RISC-V JIT implements > > all atomic operations except BPF_CMPXCHG with relaxed ordering. > > I know that the BPF memory model is in the works and we currently don't > have a way to make all the JITs consistent. But as far as atomic > operations are concerned here are my observations: > ... > > > 3. POWERPC > ------- > > JIT is emitting all atomic instructions with relaxed ordering. It > implements atomic operations using LL and SC instructions, we need to > emit "sync" instructions before and after this sequence to make it > follow the LKMM. This is how the kernel is doing it. Indeed - good find! > > Naveen, can you ack this? if this is the correct thing to do, I will > send a patch. Please do. Thanks, Naveen
