Puranjay Mohan <puranjay@xxxxxxxxxx> writes:
> The BPF atomic operations with the BPF_FETCH modifier along with
> BPF_XCHG and BPF_CMPXCHG are fully ordered but the RISC-V JIT implements
> all atomic operations except BPF_CMPXCHG with relaxed ordering.
I know that the BPF memory model is in the works and we currently don't
have a way to make all the JITs consistent. But as far as atomic
operations are concerned here are my observations:
1. ARM64 and x86
-------------
JITs are following the LKMM, where:
Any operation with BPF_FETCH, BPF_CMPXCHG, and BPF_XCHG is fully
ordered.
On x86, this is by the virtue of its memory model where locked
instructions are fully ordered. ARM64 is emitting explicit instructions
to make sure the above are fully ordered.
2. RISCV64
-------
JIT was emitting all atomic instructions with relaxed ordering, the
above patch fixes it to follow LKMM.
3. POWERPC
-------
JIT is emitting all atomic instructions with relaxed ordering. It
implements atomic operations using LL and SC instructions, we need to
emit "sync" instructions before and after this sequence to make it
follow the LKMM. This is how the kernel is doing it.
Naveen, can you ack this? if this is the correct thing to do, I will
send a patch.
4. S390
----
Ilya, can you help with this?
I see that the kernel is emitting "bcr 14,0" after "laal|laalg" but the
JIT is not.
5. Loongarch
---------
Tiezhu, can you help with this?
I see that the JIT is using am*.{w/d} instructions for all atomic
accesses. I see that there are am*_db.{w/d} instructions in the ISA that
also implement the data barrier function with the atomic op. Maybe
these need to used for BPF_FETCH, BPF_XCHG, and BPF_CMPXCHG as the
kernel is using them for arch_atomic_fetch_add() etc.
Thanks,
Puranjay
