On Thu, Feb 28, 2019 at 6:54 AM Yonghong Song <yhs@xxxxxx> wrote: > > > > On 2/27/19 12:50 PM, Jiong Wang wrote: > > Like the other load/store instructions, "w" register is prefered when > > disassembling BPF_STX | BPF_W | BPF_XADD under sub-register mode. > > > > Signed-off-by: Jiong Wang <jiong.wang@xxxxxxxxxxxxx> > > --- > > lib/Target/BPF/Disassembler/BPFDisassembler.cpp | 3 ++- > > test/MC/BPF/load-store-32.s | 3 +++ > > 2 files changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/lib/Target/BPF/Disassembler/BPFDisassembler.cpp b/lib/Target/BPF/Disassembler/BPFDisassembler.cpp > > index ed09e44..c5be7cb 100644 > > --- a/lib/Target/BPF/Disassembler/BPFDisassembler.cpp > > +++ b/lib/Target/BPF/Disassembler/BPFDisassembler.cpp > > @@ -171,9 +171,10 @@ DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, > > if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; > > > > uint8_t InstClass = getInstClass(Insn); > > + uint8_t InstMode = getInstMode(Insn); > > if ((InstClass == BPF_LDX || InstClass == BPF_STX) && > > getInstSize(Insn) != BPF_DW && > > - getInstMode(Insn) == BPF_MEM && > > + (InstMode == BPF_MEM || InstMode == BPF_XADD) && > > STI.getFeatureBits()[BPF::ALU32]) > > Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address, > > This change triggered the unit test MC/BPF/insn-unit.s failure. > > Exit Code: 1 > > Command Output (stderr): > -- > /data/users/yhs/work/llvm/test/MC/BPF/insn-unit.s:60:11: error: CHECK: > expected string not found in input > // CHECK: c3 92 10 00 00 00 00 00 lock *(u32 *)(r2 + 16) += r9 > ^ > <stdin>:25:2: note: scanning from here > 22: c3 92 10 00 00 00 00 00 lock *(u32 *)(r2 + 16) += w9 > ^ > <stdin>:25:6: note: possible intended match here > 22: c3 92 10 00 00 00 00 00 lock *(u32 *)(r2 + 16) += w9 > ^ > probably objdump -mattr=+alu32 decoding issue. Ah, apology. The disassembler change was added at last minute and I was too confident with the trival change that forgetting to run full regression. Yes, the issue is the BPF_W insn will show in "w" register format. So, need the following minior change on the testcase: diff --git a/test/MC/BPF/insn-unit.s b/test/MC/BPF/insn-unit.s index c61c002..ff56cfa 100644 --- a/test/MC/BPF/insn-unit.s +++ b/test/MC/BPF/insn-unit.s @@ -57,7 +57,8 @@ lock *(u32 *)(r2 + 16) += r9 // BPF_STX | BPF_W | BPF_XADD lock *(u64 *)(r3 - 30) += r10 // BPF_STX | BPF_DW | BPF_XADD -// CHECK: c3 92 10 00 00 00 00 00 lock *(u32 *)(r2 + 16) += r9 +// CHECK-64: c3 92 10 00 00 00 00 00 lock *(u32 *)(r2 + 16) += r9 +// CHECK-32: c3 92 10 00 00 00 00 00 lock *(u32 *)(r2 + 16) += w9 // CHECK: db a3 e2 ff 00 00 00 00 lock *(u64 *)(r3 - 30) += r10 // ======== BPF_JMP Class ======== Regards, Jiong
