[PATCH LLVM 3/3] bpf: disassembler support for XADD under sub-register mode

[Jiong Wang <jiong.wang@xxxxxxxxxxxxx>]

Like the other load/store instructions, "w" register is prefered when
disassembling BPF_STX | BPF_W | BPF_XADD under sub-register mode.

Signed-off-by: Jiong Wang <jiong.wang@xxxxxxxxxxxxx>
---
 lib/Target/BPF/Disassembler/BPFDisassembler.cpp | 3 ++-
 test/MC/BPF/load-store-32.s                     | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/lib/Target/BPF/Disassembler/BPFDisassembler.cpp b/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
index ed09e44..c5be7cb 100644
--- a/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
+++ b/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
@@ -171,9 +171,10 @@ DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
   if (Result == MCDisassembler::Fail) return MCDisassembler::Fail;
 
   uint8_t InstClass = getInstClass(Insn);
+  uint8_t InstMode = getInstMode(Insn);
   if ((InstClass == BPF_LDX || InstClass == BPF_STX) &&
       getInstSize(Insn) != BPF_DW &&
-      getInstMode(Insn) == BPF_MEM &&
+      (InstMode == BPF_MEM || InstMode == BPF_XADD) &&
       STI.getFeatureBits()[BPF::ALU32])
     Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address,
                                this, STI);
diff --git a/test/MC/BPF/load-store-32.s b/test/MC/BPF/load-store-32.s
index 73ed9fc..be576d2 100644
--- a/test/MC/BPF/load-store-32.s
+++ b/test/MC/BPF/load-store-32.s
@@ -17,9 +17,12 @@
   *(u8 *)(r0 + 0) = w7    // BPF_STX | BPF_B
   *(u16 *)(r1 + 8) = w8   // BPF_STX | BPF_H
   *(u32 *)(r2 + 16) = w9  // BPF_STX | BPF_W
+  lock *(u32 *)(r2 + 16) += w9  // BPF_STX | BPF_W | BPF_XADD
 // CHECK-32: 73 70 00 00 00 00 00 00 	*(u8 *)(r0 + 0) = w7
 // CHECK-32: 6b 81 08 00 00 00 00 00 	*(u16 *)(r1 + 8) = w8
 // CHECK-32: 63 92 10 00 00 00 00 00 	*(u32 *)(r2 + 16) = w9
+// CHECK-32: c3 92 10 00 00 00 00 00 	lock *(u32 *)(r2 + 16) += w9
 // CHECK: 73 70 00 00 00 00 00 00 	*(u8 *)(r0 + 0) = r7
 // CHECK: 6b 81 08 00 00 00 00 00 	*(u16 *)(r1 + 8) = r8
 // CHECK: 63 92 10 00 00 00 00 00 	*(u32 *)(r2 + 16) = r9
+// CHECK: c3 92 10 00 00 00 00 00 	lock *(u32 *)(r2 + 16) += r9
-- 
2.7.4