Re: [PATCH 1/2] drm/amd/display: Do not set drr on pipe commit

[Hamza Mahfooz <hamza.mahfooz@xxxxxxx>]

On 7/5/23 14:07, Aurabindo Pillai wrote:
> From: Wesley Chalmers <Wesley.Chalmers@xxxxxxx>
>
> [WHY]
> Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
> pipe commit can cause underflow.
>
> [HOW]
> Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets
> optimized_required.
>
> This change expects that Freesync requests are blocked when
> optimized_required is true.
>
> Fixes: de1da2f7fe25 ("drm/amd/display: Add monitor specific edid quirk")
> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@xxxxxxx>
> Signed-off-by: Wesley Chalmers <Wesley.Chalmers@xxxxxxx>
> Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>

This series is:

Acked-by: Hamza Mahfooz <hamza.mahfooz@xxxxxxx>

> ---
>   drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 ++++++
>   drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 7 +++++++
>   2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> index 4492bc2392b6..dba7eab9a2c4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> @@ -2123,6 +2123,12 @@ void dcn20_optimize_bandwidth(
>   	if (hubbub->funcs->program_compbuf_size)
>   		hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
>   
> +	if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
> +		dc_dmub_srv_p_state_delegate(dc,
> +			true, context);
> +		context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
> +	}
> +
>   	dc->clk_mgr->funcs->update_clocks(
>   			dc->clk_mgr,
>   			context,
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index bf8864bc8a99..7d38977f09a6 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -951,11 +951,18 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
>   void dcn30_prepare_bandwidth(struct dc *dc,
>   			     struct dc_state *context)
>   {
> +	if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
> +		dc->optimized_required = true;
> +		context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
> +	}
> +
>   	if (dc->clk_mgr->dc_mode_softmax_enabled)
>   		if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
>   				context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
>   			dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
>   
>   	dcn20_prepare_bandwidth(dc, context);
> +
> +	dc_dmub_srv_p_state_delegate(dc, false, context);
>   }
>   
--
Hamza