>
> [AMD Official Use Only - General]
>
>
>
> > -----Original Message-----
> > From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of
> > Jonatas Esteves
> > Sent: Tuesday, November 15, 2022 7:13 AM
> > To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> > Cc: Jonatas Esteves <jntesteves@xxxxxxxxx>
> > Subject: [PATCH] drm/amd/pm: Fix output of pp_od_clk_voltage
> >
> > Printing the other clock types should not be conditioned on being able
> > to print OD_SCLK. Some GPUs currently have limited capability of only
> > printing a subset of these.
> >
> > Since this condition was introduced in v5.18-rc1, reading from
> > `pp_od_clk_voltage` has been returning empty on the Asus ROG Strix G15
> > (2021).
> What's the output then with this patch applied?
```
$ cat /sys/class/drm/card1/device/pp_od_clk_voltage
OD_VDDGFX_OFFSET:
0mV
OD_RANGE:
```
Changing OD_VDDGFX_OFFSET works for this chip. Changing GFXCLK_LIMITS
and UCLK_LIMITS is not supported as per the checks in
sienna_cichlid_ppt.c -> sienna_cichlid_od_edit_dpm_table()
> Meanwhile can you show me the 'lspci' output( I wonder which asic is used on your system)?
The ASIC is a RX 6800M / NAVI22 / Navy Flounder / IP_VERSION(11, 0, 11)
```
$ lspci
00:00.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir/Cezanne
Root Complex
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Renoir/Cezanne IOMMU
00:01.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe
Dummy Host Bridge
00:01.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe GPP Bridge
00:02.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe
Dummy Host Bridge
00:02.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir/Cezanne
PCIe GPP Bridge
00:02.2 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir/Cezanne
PCIe GPP Bridge
00:02.4 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir/Cezanne
PCIe GPP Bridge
00:08.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe
Dummy Host Bridge
00:08.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir Internal
PCIe GPP Bridge to Bus
00:14.0 SMBus: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller (rev 51)
00:14.3 ISA bridge: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge (rev 51)
00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data
Fabric; Function 0
00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data
Fabric; Function 1
00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data
Fabric; Function 2
00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data
Fabric; Function 3
00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data
Fabric; Function 4
00:18.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data
Fabric; Function 5
00:18.6 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data
Fabric; Function 6
00:18.7 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data
Fabric; Function 7
01:00.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL
Upstream Port of PCI Express Switch (rev c3)
02:00.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL
Downstream Port of PCI Express Switch
03:00.0 Display controller: Advanced Micro Devices, Inc. [AMD/ATI]
Navi 22 [Radeon RX 6700/6700 XT/6750 XT / 6800M] (rev c3)
03:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Navi
21/23 HDMI/DP Audio Controller
04:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15)
05:00.0 Network controller: MEDIATEK Corp. MT7921 802.11ax PCI Express
Wireless Network Adapter
06:00.0 Non-Volatile memory controller: Intel Corporation Device f1aa (rev 03)
07:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
[AMD/ATI] Cezanne [Radeon Vega Series / Radeon Vega Mobile Series]
(rev c4)
07:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Renoir
Radeon High Definition Audio Controller
07:00.2 Encryption controller: Advanced Micro Devices, Inc. [AMD]
Family 17h (Models 10h-1fh) Platform Security Processor
07:00.3 USB controller: Advanced Micro Devices, Inc. [AMD]
Renoir/Cezanne USB 3.1
07:00.4 USB controller: Advanced Micro Devices, Inc. [AMD]
Renoir/Cezanne USB 3.1
07:00.5 Multimedia controller: Advanced Micro Devices, Inc. [AMD]
ACP/ACP3X/ACP6x Audio Coprocessor (rev 01)
07:00.6 Audio device: Advanced Micro Devices, Inc. [AMD] Family
17h/19h HD Audio Controller
```
Here are some SMU initialization logs I think might also be important:
```
[ 970.119696] amdgpu 0000:03:00.0: amdgpu: SMU is resuming...
[ 970.119701] amdgpu 0000:03:00.0: amdgpu: smu driver if version =
0x0000000e, smu fw if version = 0x00000012, smu fw program = 0,
version = 0x00413700 (65.55.0)
[ 970.119704] amdgpu 0000:03:00.0: amdgpu: SMU driver if version not matched
[ 970.119751] amdgpu 0000:03:00.0: amdgpu: use vbios provided pptable
[ 970.183486] amdgpu 0000:03:00.0: amdgpu: SMU is resumed successfully!
```
Thanks for your attention on this.
Jonatas
>
> BR
> Evan
> >
> > Fixes: 79c65f3fcbb1 ("drm/amd/pm: do not expose power implementation
> > details to amdgpu_pm.c")
> > ---
> > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 12 +++++-------
> > 1 file changed, 5 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > index 236657eece47..9d364bbc78e1 100644
> > --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> > @@ -869,13 +869,11 @@ static ssize_t
> > amdgpu_get_pp_od_clk_voltage(struct device *dev,
> > }
> > if (ret == -ENOENT) {
> > size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
> > - if (size > 0) {
> > - size += amdgpu_dpm_print_clock_levels(adev,
> > OD_MCLK, buf + size);
> > - size += amdgpu_dpm_print_clock_levels(adev,
> > OD_VDDC_CURVE, buf + size);
> > - size += amdgpu_dpm_print_clock_levels(adev,
> > OD_VDDGFX_OFFSET, buf + size);
> > - size += amdgpu_dpm_print_clock_levels(adev,
> > OD_RANGE, buf + size);
> > - size += amdgpu_dpm_print_clock_levels(adev,
> > OD_CCLK, buf + size);
> > - }
> > + size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK,
> > buf + size);
> > + size += amdgpu_dpm_print_clock_levels(adev,
> > OD_VDDC_CURVE, buf + size);
> > + size += amdgpu_dpm_print_clock_levels(adev,
> > OD_VDDGFX_OFFSET, buf + size);
> > + size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE,
> > buf + size);
> > + size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK,
> > buf + size);
> > }
> >
> > if (size == 0)
> > --
> > 2.30.2
