On Sun, Jun 5, 2022 at 10:39 PM ZhenGuo Yin <zhenguo.yin@xxxxxxx> wrote:
>
> The scratch register should be accessed through MMIO instead of RLCG
> in SRIOV, since it being used in RLCG register access function.
>
> Fixes: 0e1314781b9c("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
> Signed-off-by: ZhenGuo Yin <zhenguo.yin@xxxxxxx>
Won't gfx9 and gfx11 need similar fixes?
Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index c5f46d264b23..ecbaf92759b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3780,11 +3780,12 @@ static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
> static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> + uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
> uint32_t tmp = 0;
> unsigned i;
> int r;
>
> - WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
> + WREG32(scratch, 0xCAFEDEAD);
> r = amdgpu_ring_alloc(ring, 3);
> if (r) {
> DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
> @@ -3793,13 +3794,13 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
> }
>
> amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
> - amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0) -
> + amdgpu_ring_write(ring, scratch -
> PACKET3_SET_UCONFIG_REG_START);
> amdgpu_ring_write(ring, 0xDEADBEEF);
> amdgpu_ring_commit(ring);
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
> + tmp = RREG32(scratch);
> if (tmp == 0xDEADBEEF)
> break;
> if (amdgpu_emu_mode == 1)
> --
> 2.35.1
>
