[AMD Official Use Only - General]
Hi, @Christian König
Added a local variable to store register offset according to your comments.
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of ZhenGuo Yin
Sent: Monday, June 6, 2022 10:39 AM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Yin, ZhenGuo (Chris) <ZhenGuo.Yin@xxxxxxx>; Chen, JingWen (Wayne) <JingWen.Chen2@xxxxxxx>
Subject: [PATCH v2] drm/amdgpu: fix scratch register access method in SRIOV
The scratch register should be accessed through MMIO instead of RLCG in SRIOV, since it being used in RLCG register access function.
Fixes: 0e1314781b9c("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
Signed-off-by: ZhenGuo Yin <zhenguo.yin@xxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index c5f46d264b23..ecbaf92759b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3780,11 +3780,12 @@ static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) {
struct amdgpu_device *adev = ring->adev;
+ uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
uint32_t tmp = 0;
unsigned i;
int r;
- WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
+ WREG32(scratch, 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 3);
if (r) {
DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", @@ -3793,13 +3794,13 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
}
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
- amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0) -
+ amdgpu_ring_write(ring, scratch -
PACKET3_SET_UCONFIG_REG_START);
amdgpu_ring_write(ring, 0xDEADBEEF);
amdgpu_ring_commit(ring);
for (i = 0; i < adev->usec_timeout; i++) {
- tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
+ tmp = RREG32(scratch);
if (tmp == 0xDEADBEEF)
break;
if (amdgpu_emu_mode == 1)
--
2.35.1
--- Begin Message ---
- To: "Yin, ZhenGuo (Chris)" <ZhenGuo.Yin@xxxxxxx>, "amd-gfx@xxxxxxxxxxxxxxxxxxxxx" <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
- Subject: Re: [PATCH] drm/amdgpu: fix scratch register access method in SRIOV
- From: Christian König <ckoenig.leichtzumerken@xxxxxxxxx>
- Date: Wed, 1 Jun 2022 11:48:11 +0000
- Cc: "Chen, JingWen (Wayne)" <JingWen.Chen2@xxxxxxx>
- In-reply-to: <20220601072732.2773139-1-zhenguo.yin@amd.com>
- References: <20220601072732.2773139-1-zhenguo.yin@amd.com>
Am 01.06.22 um 09:27 schrieb ZhenGuo Yin:
> The scratch register should be accessed through MMIO instead of RLCG
> in SRIOV, since it being used in RLCG register access function.
>
> Fixes: 0e1314781b9c("drm/amdgpu: nuke dynamic gfx scratch reg allocation")
Maybe better but the register offset into a local constant then.
Apart from that looks good to me.
Regards,
Christian.
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index c5f46d264b23..8331e0c5e18e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3784,7 +3784,7 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
> unsigned i;
> int r;
>
> - WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
> + WREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0), 0xCAFEDEAD);
> r = amdgpu_ring_alloc(ring, 3);
> if (r) {
> DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
> @@ -3799,7 +3799,7 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
> amdgpu_ring_commit(ring);
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
> + tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0));
> if (tmp == 0xDEADBEEF)
> break;
> if (amdgpu_emu_mode == 1)
--- End Message ---
