From: Samson Tam <Samson.Tam@xxxxxxx>
Update base.dprefclk_khz to match result from dcn32_dump_clk_registers()
Signed-off-by: Samson Tam <Samson.Tam@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
.../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index f147c65137c6..bd2352e61040 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -598,7 +598,11 @@ void dcn32_clk_mgr_construct(
clk_mgr->ss_on_dprefclk = false;
clk_mgr->dfs_ref_freq_khz = 100000;
- clk_mgr->base.dprefclk_khz = 717000; /* Changed as per DCN3.2_clock_frequency doc */
+ /* Changed from DCN3.2_clock_frequency doc to match
+ * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz /
+ * dprefclk DID divider
+ */
+ clk_mgr->base.dprefclk_khz = 716666;
clk_mgr->dccg->ref_dtbclk_khz = 268750;
/* integer part is now VCO frequency in kHz */
@@ -612,8 +616,7 @@ void dcn32_clk_mgr_construct(
}
if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
- //ASSERT(clk_mgr->base.dprefclk_khz == clk_mgr->base.boot_snapshot.dprefclk);
- //clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
+ clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
}
dcn32_clock_read_ss_info(clk_mgr);
--
2.35.3
