Re: [PATCH 3/6] drm/amd/display: configure dc hw resource for DCN 3.1.6

[Leo Li <sunpeng.li@xxxxxxx>]

On 2022-02-15 16:44, Alex Deucher wrote:
> From: Prike Liang <Prike.Liang@xxxxxxx>
>
> - set DC version
> - add construct/destroy dc clock management function
> - register dcn interrupt handler
>
> Signed-off-by: Prike Liang <Prike.Liang@xxxxxxx>
> Acked-by: Leo Li <sunpeng.li@xxxxxxx
Reviewed-by: Leo Li <sunpeng.li@xxxxxxx>

Thanks.

> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 14 +++++++++++++-
>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c |  3 ++-
>   .../amd/display/dc/bios/command_table_helper2.c    |  1 +
>   drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c   |  4 +++-
>   drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  4 ++++
>   drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c   |  1 +
>   drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c |  1 +
>   drivers/gpu/drm/amd/display/include/dal_asic_id.h  |  6 +++++-
>   drivers/gpu/drm/amd/display/include/dal_types.h    |  1 +
>   9 files changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 10ca3fc6d91e..a4254357bf5f 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -114,6 +114,8 @@ MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
>   MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
>   #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
>   MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
> +#define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
> +MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
>   
>   #define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"
>   MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
> @@ -1801,6 +1803,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
>   		case IP_VERSION(3, 0, 1):
>   		case IP_VERSION(3, 1, 2):
>   		case IP_VERSION(3, 1, 3):
> +		case IP_VERSION(3, 1, 6):
>   			return 0;
>   		default:
>   			break;
> @@ -1916,6 +1919,10 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
>   		dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
>   		fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
>   		break;
> +	case IP_VERSION(3, 1, 6):
> +		dmub_asic = DMUB_ASIC_DCN31B;
> +		fw_name_dmub = FIRMWARE_DCN316_DMUB;
> +		break;
>   
>   	default:
>   		/* ASIC doesn't support DMUB. */
> @@ -4224,6 +4231,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
>   	case IP_VERSION(3, 0, 0):
>   	case IP_VERSION(3, 1, 2):
>   	case IP_VERSION(3, 1, 3):
> +	case IP_VERSION(3, 1, 6):
>   	case IP_VERSION(2, 1, 0):
>   		if (register_outbox_irq_handlers(dm->adev)) {
>   			DRM_ERROR("DM: Failed to initialize IRQ\n");
> @@ -4240,6 +4248,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
>   		switch (adev->ip_versions[DCE_HWIP][0]) {
>   		case IP_VERSION(3, 1, 2):
>   		case IP_VERSION(3, 1, 3):
> +		case IP_VERSION(3, 1, 6):
>   			psr_feature_enabled = true;
>   			break;
>   		default:
> @@ -4356,6 +4365,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
>   		case IP_VERSION(3, 0, 1):
>   		case IP_VERSION(3, 1, 2):
>   		case IP_VERSION(3, 1, 3):
> +		case IP_VERSION(3, 1, 6):
>   			if (dcn10_register_irq_handlers(dm->adev)) {
>   				DRM_ERROR("DM: Failed to initialize IRQ\n");
>   				goto fail;
> @@ -4541,6 +4551,7 @@ static int dm_early_init(void *handle)
>   		case IP_VERSION(2, 1, 0):
>   		case IP_VERSION(3, 1, 2):
>   		case IP_VERSION(3, 1, 3):
> +		case IP_VERSION(3, 1, 6):
>   			adev->mode_info.num_crtc = 4;
>   			adev->mode_info.num_hpd = 4;
>   			adev->mode_info.num_dig = 4;
> @@ -5213,6 +5224,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
>   	case AMDGPU_FAMILY_NV:
>   	case AMDGPU_FAMILY_VGH:
>   	case AMDGPU_FAMILY_YC:
> +	case AMDGPU_FAMILY_GC_10_3_7:
>   		if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
>   			add_gfx10_3_modifiers(adev, mods, &size, &capacity);
>   		else
> @@ -6179,7 +6191,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
>   	if (stream->link && stream->link->local_sink)
>   		max_dsc_target_bpp_limit_override =
>   			stream->link->local_sink->edid_caps.panel_patch.max_dsc_target_bpp_limit;
> -	
> +
>   	/* Set DSC policy according to dsc_clock_en */
>   	dc_dsc_policy_set_enable_dsc_when_not_needed(
>   		aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
> index 5bfdc66b5867..8709827b69ad 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
> @@ -663,7 +663,8 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct
>   		INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate);
>   
>   		hdcp_work[i].hdcp.config.psp.handle = &adev->psp;
> -		if (dc->ctx->dce_version == DCN_VERSION_3_1)
> +		if (dc->ctx->dce_version == DCN_VERSION_3_1 ||
> +		    dc->ctx->dce_version == DCN_VERSION_3_16)
>   			hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1;
>   		hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);
>   		hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c;
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> index eedc553f340e..d0fcfb158436 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> @@ -76,6 +76,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
>   	case DCN_VERSION_3_02:
>   	case DCN_VERSION_3_03:
>   	case DCN_VERSION_3_1:
> +	case DCN_VERSION_3_16:
>   		*h = dal_cmd_tbl_helper_dce112_get_table2();
>   		return true;
>   #endif
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> index 9200c8ce02ba..a707d07d5197 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> @@ -278,7 +278,8 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
>   			return &clk_mgr->base.base;
>   		}
>   		break;
> -	case FAMILY_YELLOW_CARP: {
> +	case FAMILY_YELLOW_CARP:
> +	case AMDGPU_FAMILY_GC_10_3_7:{
>   		struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
>   
>   		if (clk_mgr == NULL) {
> @@ -322,6 +323,7 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
>   		break;
>   
>   	case FAMILY_YELLOW_CARP:
> +	case AMDGPU_FAMILY_GC_10_3_7:
>   			dcn31_clk_mgr_destroy(clk_mgr);
>   		break;
>   
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index 71b393194c55..ed6b0eec1b68 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -155,6 +155,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>   		if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev))
>   			dc_version = DCN_VERSION_3_1;
>   		break;
> +	case AMDGPU_FAMILY_GC_10_3_7:
> +		if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
> +			dc_version = DCN_VERSION_3_16;
> +		break;
>   #endif
>   
>   	default:
> diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
> index 5029d4e42dbf..c9ee212b2e80 100644
> --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
> +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
> @@ -114,6 +114,7 @@ bool dal_hw_factory_init(
>   	case DCN_VERSION_3_02:
>   	case DCN_VERSION_3_03:
>   	case DCN_VERSION_3_1:
> +	case DCN_VERSION_3_16:
>   		dal_hw_factory_dcn30_init(factory);
>   		return true;
>   #endif
> diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
> index 904bd30bed68..42adba630125 100644
> --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
> +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
> @@ -109,6 +109,7 @@ bool dal_hw_translate_init(
>   	case DCN_VERSION_3_02:
>   	case DCN_VERSION_3_03:
>   	case DCN_VERSION_3_1:
> +	case DCN_VERSION_3_16:
>   		dal_hw_translate_dcn30_init(translate);
>   		return true;
>   #endif
> diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> index e672be6327cb..79f6a9ddb4bd 100644
> --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> @@ -227,7 +227,6 @@ enum {
>   #endif
>   
>   #define FAMILY_YELLOW_CARP                     146
> -
>   #define YELLOW_CARP_A0 0x01
>   #define YELLOW_CARP_B0 0x20
>   #define YELLOW_CARP_UNKNOWN 0xFF
> @@ -236,6 +235,11 @@ enum {
>   #define ASICREV_IS_YELLOW_CARP(eChipRev) ((eChipRev >= YELLOW_CARP_A0) && (eChipRev < YELLOW_CARP_UNKNOWN))
>   #endif
>   
> +#define AMDGPU_FAMILY_GC_10_3_7                151
> +#define GC_10_3_7_A0 0x01
> +#define GC_10_3_7_UNKNOWN 0xFF
> +
> +#define ASICREV_IS_GC_10_3_7(eChipRev) ((eChipRev >= GC_10_3_7_A0) && (eChipRev < GC_10_3_7_UNKNOWN))
>   
>   /*
>    * ASIC chip ID
> diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
> index 012b7c61798c..8ddb25519880 100644
> --- a/drivers/gpu/drm/amd/display/include/dal_types.h
> +++ b/drivers/gpu/drm/amd/display/include/dal_types.h
> @@ -57,6 +57,7 @@ enum dce_version {
>   	DCN_VERSION_3_02,
>   	DCN_VERSION_3_03,
>   	DCN_VERSION_3_1,
> +	DCN_VERSION_3_16,
>   	DCN_VERSION_MAX
>   };
>