Re: [PATCH 16/27] drm/amd/display: increase Z9 latency to workaround underflow in Z9

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Dear Nicholas, dear Eric, dear Augustin,


Am 18.10.21 um 19:14 schrieb Kazlauskas, Nicholas:
On 2021-10-15 7:53 p.m., Mike Lothian wrote:
This patch seems to change z8 - not that I know what z8 or z9 are

It's a little misleading but the patch and terminology is correct.

Z9 is the usecase for these watermarks even if the calculation is shared with Z8/Z9.

It’d be great to have that in the commit message.


Kind regards,

Paul

On Fri, 15 Oct 2021 at 19:44, Agustin Gutierrez wrote:

From: Eric Yang <Eric.Yang2@xxxxxxx>

[Why]
Z9 latency is higher than when we originally tuned the watermark
parameters, causing underflow. Increasing the value until the latency
issues is resolved.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@xxxxxxx>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@xxxxxxx>
Signed-off-by: Eric Yang <Eric.Yang2@xxxxxxx>
---
  drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index c9d3d691f4c6..12ebd9f8912f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -222,8 +222,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
         .num_states = 5,
         .sr_exit_time_us = 9.0,
         .sr_enter_plus_exit_time_us = 11.0,
-       .sr_exit_z8_time_us = 402.0,
-       .sr_enter_plus_exit_z8_time_us = 520.0,
+       .sr_exit_z8_time_us = 442.0,
+       .sr_enter_plus_exit_z8_time_us = 560.0,
         .writeback_latency_us = 12.0,
         .dram_channel_width_bytes = 4,
         .round_trip_ping_latency_dcfclk_cycles = 106,
--
2.25.1





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