Thanks. Will modify to remove the check since all SDMA 4_x share the same setting logic.
Thanks,
Feifei
-----Original Message-----
From: Lazar, Lijo <Lijo.Lazar@xxxxxxx>
Sent: Thursday, March 4, 2021 1:37 PM
To: Alex Deucher <alexdeucher@xxxxxxxxx>; Xu, Feifei <Feifei.Xu@xxxxxxx>
Cc: amd-gfx list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
Subject: RE: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
[AMD Public Use]
There shouldn't be any check based on ASIC type. If a check is required, it should be based on AMD_CG_SUPPORT_SDMA_MGCG and AMD_CG_SUPPORT_SDMA_LS. We set the flags appropriately for each ASIC in soc15.
Thanks,
Lijo
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Alex Deucher
Sent: Thursday, March 4, 2021 10:50 AM
To: Xu, Feifei <Feifei.Xu@xxxxxxx>
Cc: amd-gfx list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
On Wed, Mar 3, 2021 at 11:44 PM Xu, Feifei <Feifei.Xu@xxxxxxx> wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Thanks. The VegaM still need to be rule out.
VegaM is SDMA 3.x.
Alex
>
> Thanks,
> Feifei
>
> -----Original Message-----
> From: Alex Deucher <alexdeucher@xxxxxxxxx>
> Sent: Thursday, March 4, 2021 12:12 PM
> To: Xu, Feifei <Feifei.Xu@xxxxxxx>
> Cc: amd-gfx list <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
> Subject: Re: [PATCH] drm/amdgpu: simplify the sdma 4_x MGCG/MGLS logic.
>
> On Wed, Mar 3, 2021 at 10:58 PM Feifei Xu <Feifei.Xu@xxxxxxx> wrote:
> >
> > SDMA 4_x asics share the same MGCG/MGLS setting.
> >
> > Signed-off-by: Feifei Xu <Feifei.Xu@xxxxxxx>
> > ---
> > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +-----------
> > 1 file changed, 1 insertion(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > index 3bede8a70d7e..f46169c048fd 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> > @@ -2271,21 +2271,11 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
> > if (amdgpu_sriov_vf(adev))
> > return 0;
> >
> > - switch (adev->asic_type) {
> > - case CHIP_VEGA10:
> > - case CHIP_VEGA12:
> > - case CHIP_VEGA20:
> > - case CHIP_RAVEN:
> > - case CHIP_ARCTURUS:
> > - case CHIP_RENOIR:
> > - case CHIP_ALDEBARAN:
> > + if (adev->asic_type >= CHIP_VEGA10){
>
> Need a space between ) and {. That said, do we even need to check the asic type here at all? I think this applies to all chips that have sdma4.
>
> Alex
>
> > sdma_v4_0_update_medium_grain_clock_gating(adev,
> > state == AMD_CG_STATE_GATE);
> > sdma_v4_0_update_medium_grain_light_sleep(adev,
> > state == AMD_CG_STATE_GATE);
> > - break;
> > - default:
> > - break;
> > }
> > return 0;
> > }
> > --
> > 2.25.1
> >
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