Re: [PATCH] amdgpu: resize BAR0 to the maximum available size, even if it doesn't cover VRAM

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I demand that Christian König may or may not have written...

> Am 11.12.20 um 02:42 schrieb Darren Salt:
>> I demand that Christian König may or may not have written...
> [SNIP]

> Well I did wrote that :)

“did write”, surely…

>> I used dd:
>> # dd if=/sys/kernel/debug/dri/0/amdgpu_vram bs=1048576 count=1 skip=6127 | hexdump -C |tail

> That won't work. amdgpu_vram uses a MMIO register pair to access VRAM which
> works even when it isn't CPU visible.

> Thinking more about it umr would probably use this as well, so that won't
> work either.

> You could try to use dd on /dev/mem with the offset of the BAR.

Looks like that's RAM accessed by physical address, so that won't work
either. And I do see dd reporting ‘bad address’.

>> Anyway I agree that a PCI subsystem quirk might be appropriated.

> I'm going to discuss AMD internally why you have such strange values in 
> the RBAR registers.

I'm thinking probably an error by somebody at Sapphire, but we'll see…

Hopefully, that'll sort it out, at least for new cards. I doubt that mine's
the only one like this, and it seems likely that most already out there won't
be updated (shoudl there be new VBIOS releases as a reault).

Anyway, I have a quirk patch written now – untested as yet, and probably
going to be changed due to other changes before I do test it.

[snip]
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