[AMD Public Use] Rather than introduce this as a generic step in amdgpu_smu, confine the work around only to sienna cichlid. For ex: this may be done just before enabling dpm with system_features control override. Thanks, Lijo -----Original Message----- From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Evan Quan Sent: Tuesday, December 8, 2020 1:58 PM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Quan, Evan <Evan.Quan@xxxxxxx> Subject: [PATCH 5/6] drm/amd/pm: wrapper for applying 2nd usb2.0 port workaround [CAUTION: External Email] 2nd usb2.0 port workaround wrapper. Change-Id: I615d8a568b1f6623a060ba5081c2d2a1235f32b9 Signed-off-by: Evan Quan <evan.quan@xxxxxxx> --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 ++++++ drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 1 + 3 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h index cb96466605d5..3d6af881f507 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h @@ -601,6 +601,7 @@ struct pptable_funcs { int (*gpo_control)(struct smu_context *smu, bool enablement); int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); + int (*notify_2nd_usb20_port)(struct smu_context *smu); }; typedef enum { diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index e6ae722ca6e6..3515203df2c5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -935,6 +935,12 @@ static int smu_smc_hw_setup(struct smu_context *smu) return ret; } + ret = smu_notify_2nd_usb20_port(smu); + if (ret) { + dev_err(adev->dev, "Failed to notify 2nd usb2.0 port!\n"); + return ret; + } + ret = smu_set_driver_table_location(smu); if (ret) { dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h index 68d9464ababc..2eaec41dc808 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h @@ -91,6 +91,7 @@ #define smu_post_init(smu) smu_ppt_funcs(post_init, 0, smu) #define smu_gpo_control(smu, enablement) smu_ppt_funcs(gpo_control, 0, smu, enablement) #define smu_set_fine_grain_gfx_freq_parameters(smu) smu_ppt_funcs(set_fine_grain_gfx_freq_parameters, 0, smu) +#define smu_notify_2nd_usb20_port(smu) smu_ppt_funcs(notify_2nd_usb20_port, 0, smu) #endif #endif -- 2.29.0 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Clijo.lazar%40amd.com%7C4e916532c7584fc543d808d89b5334b5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637430128956487556%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=BnxEAwGyn7th3u271jiCPfsc03729IfZWvMpzGwhuWY%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx