[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Evan Quan <evan.quan@xxxxxxx> -----Original Message----- From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Alex Deucher Sent: Wednesday, October 28, 2020 11:08 PM To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx> Subject: [PATCH] drm/amdgpu/powerplay: Only apply optimized mclk dpm policy on polaris Leads to improper dpm on older parts. Bug: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1353&data=04%7C01%7Cevan.quan%40amd.com%7C67c0a0638f9c4e316c5e08d87b534d94%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637394945031668072%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=vukW5jlFbTqB26IiUU7xljpRNf8muMWwh4sPQCB0IsA%3D&reserved=0 Fixes: 8d89b96fe797 ("drm/amd/powerplay: optimize the mclk dpm policy settings") Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx> --- .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 30 +++++++++++-------- 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c index 49db61a89505..d642dc95e9ea 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c @@ -1713,18 +1713,24 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) data->current_profile_setting.sclk_down_hyst = 100; data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT; data->current_profile_setting.bupdate_mclk = 1; -if (adev->gmc.vram_width == 256) { -data->current_profile_setting.mclk_up_hyst = 10; -data->current_profile_setting.mclk_down_hyst = 60; -data->current_profile_setting.mclk_activity = 25; -} else if (adev->gmc.vram_width == 128) { -data->current_profile_setting.mclk_up_hyst = 5; -data->current_profile_setting.mclk_down_hyst = 16; -data->current_profile_setting.mclk_activity = 20; -} else if (adev->gmc.vram_width == 64) { -data->current_profile_setting.mclk_up_hyst = 3; -data->current_profile_setting.mclk_down_hyst = 16; -data->current_profile_setting.mclk_activity = 20; +if (hwmgr->chip_id >= CHIP_POLARIS10) { +if (adev->gmc.vram_width == 256) { +data->current_profile_setting.mclk_up_hyst = 10; +data->current_profile_setting.mclk_down_hyst = 60; +data->current_profile_setting.mclk_activity = 25; +} else if (adev->gmc.vram_width == 128) { +data->current_profile_setting.mclk_up_hyst = 5; +data->current_profile_setting.mclk_down_hyst = 16; +data->current_profile_setting.mclk_activity = 20; +} else if (adev->gmc.vram_width == 64) { +data->current_profile_setting.mclk_up_hyst = 3; +data->current_profile_setting.mclk_down_hyst = 16; +data->current_profile_setting.mclk_activity = 20; +} +} else { +data->current_profile_setting.mclk_up_hyst = 0; +data->current_profile_setting.mclk_down_hyst = 100; +data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT; } hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; -- 2.25.4 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cevan.quan%40amd.com%7C67c0a0638f9c4e316c5e08d87b534d94%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637394945031668072%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=y0Q%2B5wPg9PnCLtSLMp8i5RdDSB6OH7WvRTRzi%2Bkx0E8%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx
