Re: [PATCH] drm/amdgpu/powerplay: Only apply optimized mclk dpm policy on polaris

[Luben Tuikov <luben.tuikov@xxxxxxx>]

Reviewed-by: Luben Tuikov <luben.tuikov@xxxxxxx>

I assume that the default ("else") case is what is wanted
by this patch and has been vetted-i.e. it what fixes it.

Regards,
Luben

On 2020-10-28 11:08, Alex Deucher wrote:
> Leads to improper dpm on older parts.
> 
> Bug: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1353&amp;data=04%7C01%7Cluben.tuikov%40amd.com%7C154766ca87eb40cce45508d87b534dba%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637394945025356066%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=RB%2FDlyoqyasJWWkmB6dL0jxzVM9Auc223YNkEmpIj54%3D&amp;reserved=0
> Fixes: 8d89b96fe797 ("drm/amd/powerplay: optimize the mclk dpm policy settings")
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
>  .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c   | 30 +++++++++++--------
>  1 file changed, 18 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> index 49db61a89505..d642dc95e9ea 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> @@ -1713,18 +1713,24 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
>  	data->current_profile_setting.sclk_down_hyst = 100;
>  	data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
>  	data->current_profile_setting.bupdate_mclk = 1;
> -	if (adev->gmc.vram_width == 256) {
> -		data->current_profile_setting.mclk_up_hyst = 10;
> -		data->current_profile_setting.mclk_down_hyst = 60;
> -		data->current_profile_setting.mclk_activity = 25;
> -	} else if (adev->gmc.vram_width == 128) {
> -		data->current_profile_setting.mclk_up_hyst = 5;
> -		data->current_profile_setting.mclk_down_hyst = 16;
> -		data->current_profile_setting.mclk_activity = 20;
> -	} else if (adev->gmc.vram_width == 64) {
> -		data->current_profile_setting.mclk_up_hyst = 3;
> -		data->current_profile_setting.mclk_down_hyst = 16;
> -		data->current_profile_setting.mclk_activity = 20;
> +	if (hwmgr->chip_id >= CHIP_POLARIS10) {
> +		if (adev->gmc.vram_width == 256) {
> +			data->current_profile_setting.mclk_up_hyst = 10;
> +			data->current_profile_setting.mclk_down_hyst = 60;
> +			data->current_profile_setting.mclk_activity = 25;
> +		} else if (adev->gmc.vram_width == 128) {
> +			data->current_profile_setting.mclk_up_hyst = 5;
> +			data->current_profile_setting.mclk_down_hyst = 16;
> +			data->current_profile_setting.mclk_activity = 20;
> +		} else if (adev->gmc.vram_width == 64) {
> +			data->current_profile_setting.mclk_up_hyst = 3;
> +			data->current_profile_setting.mclk_down_hyst = 16;
> +			data->current_profile_setting.mclk_activity = 20;
> +		}
> +	} else {
> +		data->current_profile_setting.mclk_up_hyst = 0;
> +		data->current_profile_setting.mclk_down_hyst = 100;
> +		data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
>  	}
>  	hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
>  	hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
> 

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