RE: [PATCH 3/4] drm/amd/powerplay: remove SRIOV check in SMU11

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[AMD Official Use Only - Internal Distribution Only]

[AMD Official Use Only - Internal Distribution Only]

Hi Evan,

With Kevin's previous patch, we will not create sysfs node pp_power_profile_mode under VF mode.

Brs
Wenhui

-----Original Message-----
From: Quan, Evan <Evan.Quan@xxxxxxx>
Sent: Tuesday, May 26, 2020 7:25 PM
To: Sheng, Wenhui <Wenhui.Sheng@xxxxxxx>; amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Sheng, Wenhui <Wenhui.Sheng@xxxxxxx>; Zhang, Hawking <Hawking.Zhang@xxxxxxx>
Subject: RE: [PATCH 3/4] drm/amd/powerplay: remove SRIOV check in SMU11

[AMD Official Use Only - Internal Distribution Only]

Please confirm the changes of arcturus_get_power_profile_mode() do not break SRIOV.
Since this seems skipped before but enabled now.
Other than that, the series is acked-by: Evan Quan <evan.quan@xxxxxxx>

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Wenhui Sheng
Sent: Tuesday, May 26, 2020 6:06 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
Cc: Sheng, Wenhui <Wenhui.Sheng@xxxxxxx>; Zhang, Hawking <Hawking.Zhang@xxxxxxx>
Subject: [PATCH 3/4] drm/amd/powerplay: remove SRIOV check in SMU11

We don't need SRIOV check after we enable SMC msg filter in SMU11

Signed-off-by: Wenhui Sheng <Wenhui.Sheng@xxxxxxx>
Change-Id: I14e1dc5669cb4bb2c112bc100d699bfb380574b3
Reviewed-by: Hawking Zhang <Hawking.Zhang@xxxxxxx>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c   | 159 +++++++++----------
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c |   6 +-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c   |   6 +-
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c    |  24 ---
 4 files changed, 80 insertions(+), 115 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index f7428996cc74..1e9be1dcc62b 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -563,10 +563,8 @@ int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int

 bool is_support_sw_smu(struct amdgpu_device *adev)  { -if (adev->asic_type >= CHIP_ARCTURUS) {
-      if (amdgpu_sriov_is_pp_one_vf(adev) || !amdgpu_sriov_vf(adev))
-return true;
-}
+if (adev->asic_type >= CHIP_ARCTURUS)
+return true;

 return false;
 }
@@ -1109,59 +1107,58 @@ static int smu_smc_table_hw_init(struct smu_context *smu,  return ret;

 /* smu_dump_pptable(smu); */
-if (!amdgpu_sriov_vf(adev)) {
-/*
- * Copy pptable bo in the vram to smc with SMU MSGs such as
- * SetDriverDramAddr and TransferTableDram2Smu.
- */
-ret = smu_write_pptable(smu);
-if (ret)
-return ret;
-
-/* issue Run*Btc msg */
-ret = smu_run_btc(smu);
-if (ret)
-return ret;
-ret = smu_feature_set_allowed_mask(smu);
-if (ret)
-return ret;
+/*
+ * Copy pptable bo in the vram to smc with SMU MSGs such as
+ * SetDriverDramAddr and TransferTableDram2Smu.
+ */
+ret = smu_write_pptable(smu);
+if (ret)
+return ret;

-ret = smu_system_features_control(smu, true); -if (ret) -return ret;
+/* issue Run*Btc msg */
+ret = smu_run_btc(smu);
+if (ret)
+return ret;
+ret = smu_feature_set_allowed_mask(smu);
+if (ret)
+return ret;

-if (adev->asic_type == CHIP_NAVI10) {
-if ((adev->pdev->device == 0x731f && (adev->pdev->revision == 0xc2 ||
-      adev->pdev->revision == 0xc3 ||
-      adev->pdev->revision == 0xca ||
-      adev->pdev->revision == 0xcb)) ||
-    (adev->pdev->device == 0x66af && (adev->pdev->revision == 0xf3 ||
-      adev->pdev->revision == 0xf4 ||
-      adev->pdev->revision == 0xf5 ||
-      adev->pdev->revision == 0xf6))) {
-ret = smu_disable_umc_cdr_12gbps_workaround(smu);
-if (ret) {
-pr_err("Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n"); -return ret; -} -} -}
+ret = smu_system_features_control(smu, true); if (ret) return ret;

-if (smu->ppt_funcs->set_power_source) {
-/*
- * For Navi1X, manually switch it to AC mode as PMFW
- * may boot it with DC mode.
- */
-if (adev->pm.ac_power)
-ret = smu_set_power_source(smu, SMU_POWER_SOURCE_AC); -else -ret = smu_set_power_source(smu, SMU_POWER_SOURCE_DC);
+if (adev->asic_type == CHIP_NAVI10) {
+if ((adev->pdev->device == 0x731f && (adev->pdev->revision == 0xc2 ||
+      adev->pdev->revision == 0xc3 ||
+      adev->pdev->revision == 0xca ||
+      adev->pdev->revision == 0xcb)) ||
+    (adev->pdev->device == 0x66af && (adev->pdev->revision == 0xf3 ||
+      adev->pdev->revision == 0xf4 ||
+      adev->pdev->revision == 0xf5 ||
+      adev->pdev->revision == 0xf6))) { ret =
+smu_disable_umc_cdr_12gbps_workaround(smu);
 if (ret) {
-pr_err("Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
+pr_err("Workaround failed to disable UMC CDR feature on 12Gbps
+SKU!\n");
 return ret;
 }
 }
 }
+
+if (smu->ppt_funcs->set_power_source) {
+/*
+ * For Navi1X, manually switch it to AC mode as PMFW
+ * may boot it with DC mode.
+ */
+if (adev->pm.ac_power)
+ret = smu_set_power_source(smu, SMU_POWER_SOURCE_AC); else ret =
+smu_set_power_source(smu, SMU_POWER_SOURCE_DC); if (ret) {
+pr_err("Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" :
+"DC"); return ret; } }
+
 if (adev->asic_type != CHIP_ARCTURUS) {  ret = smu_notify_display_change(smu);  if (ret) @@ -1214,9 +1211,8 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
 /*
  * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
  */
-if (!amdgpu_sriov_vf(adev)) {
-ret = smu_set_tool_table_location(smu); -}
+ret = smu_set_tool_table_location(smu);
+
 if (!smu_is_dpm_running(smu))
 pr_info("dpm has been disabled\n");

@@ -1376,9 +1372,6 @@ static int smu_hw_init(void *handle)

 static int smu_stop_dpms(struct smu_context *smu)  { -if (amdgpu_sriov_vf(smu->adev)) -return 0;
-
 return smu_system_features_control(smu, false);  }

@@ -1403,35 +1396,35 @@ static int smu_hw_fini(void *handle)

 adev->pm.dpm_enabled = false;

-if (!amdgpu_sriov_vf(adev)){
+if (!amdgpu_sriov_vf(adev)) {
 smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
+}
+
+ret = smu_stop_thermal_control(smu);
+if (ret) {
+pr_warn("Fail to stop thermal control!\n"); return ret; }

-ret = smu_stop_thermal_control(smu);
+/*
+ * For custom pptable uploading, skip the DPM features
+ * disable process on Navi1x ASICs.
+ *   - As the gfx related features are under control of
+ *     RLC on those ASICs. RLC reinitialization will be
+ *     needed to reenable them. That will cost much more
+ *     efforts.
+ *
+ *   - SMU firmware can handle the DPM reenablement
+ *     properly.
+ */
+if (!smu->uploading_custom_pp_table ||
+!((adev->asic_type >= CHIP_NAVI10) &&
+(adev->asic_type <= CHIP_NAVI12))) {
+ret = smu_stop_dpms(smu);
 if (ret) {
-pr_warn("Fail to stop thermal control!\n");
+pr_warn("Fail to stop Dpms!\n");
 return ret;
 }
-
-/*
- * For custom pptable uploading, skip the DPM features
- * disable process on Navi1x ASICs.
- *   - As the gfx related features are under control of
- *     RLC on those ASICs. RLC reinitialization will be
- *     needed to reenable them. That will cost much more
- *     efforts.
- *
- *   - SMU firmware can handle the DPM reenablement
- *     properly.
- */
-if (!smu->uploading_custom_pp_table ||
-!((adev->asic_type >= CHIP_NAVI10) &&
-(adev->asic_type <= CHIP_NAVI12))) {
-ret = smu_stop_dpms(smu);
-if (ret) {
-pr_warn("Fail to stop Dpms!\n");
-return ret;
-}
-}
 }

 kfree(table_context->driver_pptable);
@@ -1548,12 +1541,12 @@ static int smu_suspend(void *handle)

 if (!amdgpu_sriov_vf(adev)) {
 smu_i2c_eeprom_fini(smu, &adev->pm.smu_i2c);
-
-ret = smu_disable_dpm(smu);
-if (ret)
-return ret;
 }

+ret = smu_disable_dpm(smu);
+if (ret)
+return ret;
+
 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);

 if (adev->asic_type >= CHIP_NAVI10 &&
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index dcbb273674d1..70cc1c12f196 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1369,7 +1369,7 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu,  if (result)  return result;

-if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev))
+if (smu_version >= 0x360d00)
 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",  title[0], title[1], title[2], title[3], title[4], title[5],  title[6], title[7], title[8], title[9], title[10]); @@ -1386,7 +1386,7 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu,  if (workload_type < 0)  continue;

-if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev)) {
+if (smu_version >= 0x360d00) {
 result = smu_update_table(smu,
   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
   workload_type,
@@ -1401,7 +1401,7 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu,  size += sprintf(buf + size, "%2d %14s%s\n",  i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");

-if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev)) {
+if (smu_version >= 0x360d00) {
 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",  " ",  0, diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 5f7373e86d90..ef4952afb365 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1818,8 +1818,7 @@ static int navi10_get_power_limit(struct smu_context *smu,  int power_src;

 if (!smu->power_limit) {
-if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT) &&
-!amdgpu_sriov_vf(smu->adev)) {
+if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
 power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);  if (power_src < 0)  return -EINVAL; @@ -1962,9 +1961,6 @@ static int navi10_set_default_od_settings(struct smu_context *smu, bool initiali  OverDriveTable_t *od_table, *boot_od_table;  int ret = 0;

-if (amdgpu_sriov_vf(smu->adev))
-return 0;
-
 ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t));  if (ret)  return ret; diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 906bc7f2e686..3af439a77876 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -768,9 +768,6 @@ int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)  {  int ret;

-if (amdgpu_sriov_vf(smu->adev))
-return 0;
-
 ret = smu_send_smc_msg_with_param(smu,
   SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);  if (ret) @@ -814,9 +811,6 @@ int smu_v11_0_set_tool_table_location(struct smu_context *smu)  int ret = 0;  struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];

-if (amdgpu_sriov_vf(smu->adev))
-return 0;
-
 if (tool_table->mc_address) {
 ret = smu_send_smc_msg_with_param(smu,
 SMU_MSG_SetToolsDramAddrHigh,
@@ -836,9 +830,6 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)  {  int ret = 0;

-if (amdgpu_sriov_vf(smu->adev))
-return 0;
-
 if (!smu->pm_enabled)
 return ret;

@@ -853,9 +844,6 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu)  int ret = 0;  uint32_t feature_mask[2];

-if (amdgpu_sriov_vf(smu->adev))
-return 0;
-
 mutex_lock(&feature->mutex);
 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)  goto failed; @@ -884,9 +872,6 @@ int smu_v11_0_get_enabled_mask(struct smu_context *smu,  struct smu_feature *feature = &smu->smu_feature;  int ret = 0;

-if (amdgpu_sriov_vf(smu->adev) && !amdgpu_sriov_is_pp_one_vf(smu->adev))
-return 0;
-
 if (!feature_mask || num < 2)
 return -EINVAL;

@@ -942,9 +927,6 @@ int smu_v11_0_notify_display_change(struct smu_context *smu)  {  int ret = 0;

-if (amdgpu_sriov_vf(smu->adev))
-return 0;
-
 if (!smu->pm_enabled)
 return ret;

@@ -1107,9 +1089,6 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)  int ret = 0;  uint32_t max_power_limit;

-if (amdgpu_sriov_vf(smu->adev))
-return 0;
-
 max_power_limit = smu_v11_0_get_max_power_limit(smu);

 if (n > max_power_limit) {
@@ -1860,9 +1839,6 @@ int smu_v11_0_override_pcie_parameters(struct smu_context *smu)  uint32_t pcie_gen = 0, pcie_width = 0;  int ret;

-if (amdgpu_sriov_vf(smu->adev))
-return 0;
-
 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 pcie_gen = 3;
 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
--
2.17.1

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