Use words insteads of acronym for better understanding. Signed-off-by: Yong Zhao <Yong.Zhao@xxxxxxx> --- include/uapi/drm/amdgpu_drm.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index d65f9b4ba05c..0072ddb59747 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -564,15 +564,15 @@ struct drm_amdgpu_gem_op { #define AMDGPU_VM_MTYPE_MASK (0xf << 5) /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) -/* Use NC MTYPE instead of default MTYPE */ +/* Use Non Coherent MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_NC (1 << 5) -/* Use WC MTYPE instead of default MTYPE */ +/* Use Write Combine MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_WC (2 << 5) -/* Use CC MTYPE instead of default MTYPE */ +/* Use Cache Coherent MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_CC (3 << 5) -/* Use UC MTYPE instead of default MTYPE */ +/* Use UnCached MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_UC (4 << 5) -/* Use RW MTYPE instead of default MTYPE */ +/* Use Read Write MTYPE instead of default MTYPE */ #define AMDGPU_VM_MTYPE_RW (5 << 5) struct drm_amdgpu_gem_va { -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/amd-gfx