[AMD Public Use]
While you are at it, can you clean up the local defines of these registers indrivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.cdrivers/gpu/drm/amd/powerplay/smu_v12_0.cdrivers/gpu/drm/amd/amdgpu/gfx_v9_0.cand verify that the appropriate offset is used for both Renoir and raven?
I can absolutely do that tomorrow. I'd like to get my (v2) patch out though since it's gating an update to umr which an internal team is waiting on.
As for the PWR register through um how shall I say "sheer luck" it actually pans out fine. The Renoir code paths use the vega10 IP offsets and the PWR block's offset. Segment 0 of the PWR block from vega10 matches segment 1 of the SMUIO (v12) block. So on the face of it the CGCG code for renoir is "wrong" but because it's using the wrong IP table (which happens to have the right offsets) it works out alright.
int soc15_set_ip_blocks(struct amdgpu_device *adev)
{
/* Set IP register base before any HW register access */
switch (adev->asic_type) {
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_RAVEN:
case CHIP_RENOIR:
vega10_reg_base_init(adev);
break;
Strictly speaking this is wrong since renoir has its own IP offset table but because it reuses a lot of the KGD implementations from earlier hardware (and the registers happen to be at the same locations) this works out fine.
Tom
Alex
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Tom St Denis <tom.stdenis@xxxxxxx>
Sent: Wednesday, March 25, 2020 3:22 PM
To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx <amd-gfx@xxxxxxxxxxxxxxxxxxxxx>
Cc: StDenis, Tom <Tom.StDenis@xxxxxxx>
Subject: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)The PWR block was merged into the SMUIO block by revision 12 so we add
that to the smuio_12_0_0 headers.
(v2): Drop nonsensical smuio_10_0_0 header
Signed-off-by: Tom St Denis <tom.stdenis@xxxxxxx>
---
.../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++
.../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h | 5 +++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
index 327b4d09f66d..9bf73284ad73 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
@@ -24,4 +24,7 @@
#define mmSMUIO_GFX_MISC_CNTL 0x00c8
#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0
+#define mmPWR_MISC_CNTL_STATUS 0x0183
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 1
+
#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
index d815452cfd15..26556fa3d054 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
@@ -24,5 +24,10 @@
//SMUIO_GFX_MISC_CNTL
#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1
+//PWR_MISC_CNTL_STATUS
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
#endif
--
2.25.1
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